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/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-51000000-800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp-51000000-850 {
15 clock-latency-ns = <100000>;
[all …]
H A Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-216000000-750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
12 opp-suspend;
15 opp-216000000-800 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996pro.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ opp-table-cluster0;
10 /delete-node/ opp-table-cluster1;
18 cluster0_opp: opp-table-cluster0 {
19 compatible = "operating-points-v2-kryo-cpu";
20 nvmem-cells = <&speedbin_efuse>;
21 opp-shared;
23 opp-307200000 {
24 opp-hz = /bits/ 64 <307200000>;
25 opp-supported-hw = <0x70>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
26 --------------------
28 - power-domains: A phandle pointing to the PM domain specifier which provides
[all …]
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 cluster0_opp_table: opp-table-cluster0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-1008000000 {
9 opp-hz = /bits/ 64 <1008000000>;
10 opp-microvolt = <675000 675000 950000>;
11 clock-latency-ns = <40000>;
13 opp-1200000000 {
14 opp-hz = /bits/ 64 <1200000000>;
[all …]
H A Drk3588j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-extra.dtsi"
10 cluster0_opp_table: opp-table-cluster0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1200000000 {
15 opp-hz = /bits/ 64 <1200000000>;
16 opp-microvolt = <750000 750000 950000>;
17 clock-latency-ns = <40000>;
18 opp-suspend;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
39 compatible = "arm,cortex-a9";
41 clocks = <&clock CLK_ARM_CLK>;
42 clock-names = "cpu";
43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
[all …]
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
45 compatible = "arm,cortex-a9";
47 clocks = <&clock CLK_ARM_CLK>;
48 clock-names = "cpu";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
[all …]
H A Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 &clock {
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
[all …]
H A Ds8000.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <650>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <75000>;
[all …]
H A Ds8003.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include "s800-0-3.dtsi"
13 twister_opp: opp-table {
14 compatible = "operating-points-v2";
17 opp-hz = /bits/ 64 <300000000>;
18 opp-level = <1>;
19 clock-latency-ns = <500>;
22 opp-hz = /bits/ 64 <396000000>;
23 opp-level = <2>;
24 clock-latency-ns = <45000>;
[all …]
H A Dt8015.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
H A Dt8010.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
H A Ds5l8960x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <15500>;
20 opp-hz = /bits/ 64 <396000000>;
21 opp-level = <2>;
22 clock-latency-ns = <43000>;
[all …]
H A Ds5l8965x-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * target-type: J71, J72, J73
11 cyclone_opp: opp-table {
12 compatible = "operating-points-v2";
15 opp-hz = /bits/ 64 <300000000>;
16 opp-level = <1>;
17 clock-latency-ns = <10000>;
20 opp-hz = /bits/ 64 <600000000>;
21 opp-level = <2>;
22 clock-latency-ns = <49000>;
[all …]
/freebsd/sys/dts/arm64/overlays/
H A Dsun50i-h5-opp.dtso1 /dts-v1/;
4 #include <dt-bindings/clock/sun8i-h3-ccu.h>
7 compatible = "allwinner,sun50i-h5";
12 compatible = "operating-points-v2";
13 opp-shared;
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <1000000 1000000 1300000>;
18 clock-latency-ns = <244144>; /* 8 32k periods */
22 opp-hz = /bits/ 64 <648000000>;
23 opp-microvolt = <1040000 1040000 1300000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h616-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 cpu_opp_table: opp-table-cpu {
6 compatible = "allwinner,sun50i-h616-operating-points";
7 nvmem-cells = <&cpu_speed_grade>;
8 opp-shared;
10 opp-480000000 {
11 opp-hz = /bits/ 64 <480000000>;
12 opp-microvolt = <900000>;
13 clock-latency-ns = <244144>; /* 8 32k periods */
14 opp-supported-hw = <0x3f>;
[all …]
H A Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
H A Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp-480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
[all …]
H A Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/sigmastar/
H A Dmstar-infinity3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "mstar-infinity.dtsi"
10 opp-1008000000 {
11 opp-hz = /bits/ 64 <1008000000>;
12 opp-microvolt = <1000000>;
13 clock-latency-ns = <300000>;
17 opp-108000000 {
18 opp-hz = /bits/ 64 <1080000000>;
19 opp-microvolt = <1000000>;
20 clock-latency-ns = <300000>;
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl.h1 /*-
38 * Request that @p clock (or a faster clock) be enabled on behalf of
43 * @param clock Clock requested.
46 * @retval ENODEV If an unsupported clock was requested.
49 bhnd_pwrctl_request_clock(device_t dev, device_t child, bhnd_clock clock) in bhnd_pwrctl_request_clock() argument
51 return (BHND_PWRCTL_REQUEST_CLOCK(dev, child, clock)); in bhnd_pwrctl_request_clock()
55 * Return the transition latency required for @p clock in microseconds, if
58 * The BHND_CLOCK_HT latency value is suitable for use as the D11 core's
62 * @param clock The clock to be queried for transition latency.
63 * @param[out] latency On success, the transition latency of @p clock in
[all …]
H A Dbhnd_pwrctl_if.m1 #-
46 * Request that @p clock (or a faster clock) be enabled on behalf of
51 * @param clock Clock requested.
54 * @retval ENODEV If an unsupported clock was requested.
59 bhnd_clock clock;
63 * Return the transition latency required for @p clock in microseconds, if
66 * The BHND_CLOCK_HT latency value is suitable for use as the D11 core's
70 * @param clock The clock to be queried for transition latency.
71 * @param[out] latency On success, the transition latency of @p clock in
75 * @retval ENODEV If the transition latency for @p clock is not available.
[all …]

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