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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-evm-csi2-quad-tevi-ov5640.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for 4 x TEVI OV5640 MIPI Camera module on J722S-EVM board.
5 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-pinctrl.h"
15 cam0_reset_pins_default: cam0-default-reset-pins {
16 pinctrl-single,pins = <
21 cam1_reset_pins_default: cam1-default-reset-pins {
22 pinctrl-single,pins = <
[all …]
H A Dk3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for 4 x RPi Camera V2.1 on J722S-EVM board.
5 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
7 * Schematics: https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
10 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
17 cam0_reset_pins_default: cam0-default-reset-pins {
18 pinctrl-single,pins = <
23 cam1_reset_pins_default: cam1-default-reset-pins {
[all …]
H A Dk3-j721e-sk-csi2-dual-imx219.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 * on J721E SK, AM68 SK or AM69-SK board.
5 * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf
7 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
17 clk_imx219_fixed: imx219-xclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
[all …]
H A Dk3-am625-beagleplay-csi2-tevi-ov5640.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Technexion TEVI-OV5640-*-RPI - OV5640 camera module
4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
13 clk_ov5640_fixed: ov5640-xclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24000000>;
19 reg_2p8v: regulator-2p8v {
[all …]
H A Dk3-am625-beagleplay-csi2-ov5640.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
13 clk_ov5640_fixed: ov5640-xclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <12000000>;
19 reg_2p8v: regulator-2p8v {
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dbrcm,bcm2835-unicam.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/brcm,bcm2835-unicam.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
12 description: |-
14 CSI-2 or CCP2 data from image sensors or similar devices.
26 const: brcm,bcm2835-unicam
30 - description: Unicam block.
31 - description: Clock Manager Image (CMI) block.
[all …]
H A Dti,cal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
15 processing capability to connect CSI2 image-sensor modules to the
24 - ti,dra72-cal
26 - ti,dra72-pre-es2-cal
28 - ti,dra76-cal
30 - ti,am654-cal
[all …]
H A Dcdns,csi2rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10 - Maxime Ripard <mripard@kernel.org>
13 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14 lanes in input, and 4 different pixel streams in output.
19 - enum:
20 - starfive,jh7110-csi2rx
21 - ti,j721e-csi2rx
[all …]
H A Drockchip-isp1.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - fsl,imx8mp-isp
20 - rockchip,px30-cif-isp
21 - rockchip,rk3399-cif-isp
30 interrupt-names:
32 - const: isp
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon-csi-dsi.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
23 remote-endpoint = <&max96712_out0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
H A Dhihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 #include "aistarvision-mipi-adapter-2.1.dtsi"
18 clock-lanes = <0>;
19 data-lanes = <1 2>;
20 remote-endpoint = <&ov5645_ep>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
34 remote-endpoint = <&imx219_ep>;
41 pinctrl-0 = <&i2c3_pins>;
42 pinctrl-names = "default";
[all …]
H A Dwhite-hawk-csi-dsi.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the White Hawk CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
24 line-orders = <MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC
27 remote-endpoint = <&max96712_out0>;
[all …]
H A Dr8a774c0-ek874-mipi-2.1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
13 #include "aistarvision-mipi-adapter-2.1.dtsi"
16 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
17 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
38 clock-lanes = <0>;
39 data-lanes = <1 2>;
40 remote-endpoint = <&ov5645_ep>;
[all …]
H A Drz-smarc-cru-csi-ov5645.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "regulator-fixed";
12 regulator-name = "camera_vdddo";
13 regulator-min-microvolt = <1800000>;
14 regulator-max-microvolt = <1800000>;
15 regulator-always-on;
19 compatible = "regulator-fixed";
20 regulator-name = "camera_vdda";
21 regulator-min-microvolt = <2800000>;
22 regulator-max-microvolt = <2800000>;
[all …]
H A Dcondor-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Condor board with R-Car V3H
8 #include <dt-bindings/gpio/gpio.h>
23 stdout-path = "serial0:115200n8";
27 d1_8v: regulator-2 {
28 compatible = "regulator-fixed";
29 regulator-name = "D1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-boot-on;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dovti,ov7251.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
15 - Todor Tomov <todor.too@gmail.com>
25 description: XCLK Input Clock
27 clock-names:
30 clock-frequency:
31 description: Frequency of the xclk clock in Hz.
33 vdda-supply:
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-tqma8mpql-mba8mp-ras314-imx219.dtso1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/media/video-interfaces.h>
13 #include "imx8mp-pinfunc.h"
20 reg_cam: regulator-cam {
21 compatible = "regulator-fixed";
22 regulator-name = "reg_cam";
[all …]
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]

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