| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
9 The driver require a 25MHz Oscillator to function generate clock.
10 It includes PLLs, common clock function and some vendor clock for
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
23 tristate "Sophgo SG2042 Clock Generator support"
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| /linux/drivers/tty/serial/ |
| H A D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
165 /* Write Register 11 (Clock Mode control) */
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| H A D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
135 #define X1CLK 0x0 /* x1 clock mode */
136 #define X16CLK 0x40 /* x16 clock mode */
137 #define X32CLK 0x80 /* x32 clock mode */
138 #define X64CLK 0xc0 /* x64 clock mode */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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| H A D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 /* Write Register 11 (Clock Mode control) */
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| H A D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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| /linux/drivers/net/hamradio/ |
| H A D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
129 /* Write Register 11 (Clock Mode control) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
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| /linux/include/soc/fsl/qe/ |
| H A D | qe.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
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| /linux/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | xlnx,v-tc.txt | 2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
28 compatible = "xlnx,v-tc-6.1";
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| /linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
62 tristate "Clock driver for Apple SoC NCOs"
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-timecard | 18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
64 GEN1 output is from frequency generator 1
65 GEN2 output is from frequency generator 2
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| /linux/drivers/iio/frequency/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
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| /linux/Documentation/devicetree/bindings/ptp/ |
| H A D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | silabs,si544.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si544.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs SI514/SI544 clock generator
10 - Mike Looijmans <mike.looijmans@topic.nl>
13 Silicon Labs 514/544 programmable I2C clock generator. Details about the device
17 https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
22 - silabs,si514
23 - silabs,si544a
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| H A D | raspberrypi,rp1-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RaspberryPi RP1 clock generator
10 - A. della Porta <andrea.porta@suse.com>
13 The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO,
15 the clocks to drive the sub-peripherals embedded inside the chipset.
18 https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf
22 const: raspberrypi,rp1-clocks
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| H A D | adi,axi-clkgen.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
14 The axi_clkgen IP core is a software programmable clock generator,
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
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| H A D | silabs,si5341.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
10 - Mike Looijmans <mike.looijmans@topic.nl>
13 Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
14 generator.
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
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| H A D | renesas,cpg-mstp-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
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| H A D | silabs,si570.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si570.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si570/Si571/Si598/Si599 programmable I2C clock generator
10 - Soren Brinkmann <soren.brinkmann@xilinx.com>
13 Silicon Labs 570, 571, 598 and 599 programmable I2C clock generators. Details
19 https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
24 - silabs,si570
25 - silabs,si571
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| H A D | renesas,rzv2h-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
14 generation and control of clock signals for the IP modules, generation and
21 - renesas,r9a09g047-cpg # RZ/G3E
22 - renesas,r9a09g056-cpg # RZ/V2N
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| /linux/Documentation/devicetree/bindings/rng/ |
| H A D | microchip,pic32-rng.txt | 1 * Microchip PIC32 Random Number Generator
3 The PIC32 RNG provides a pseudo random number generator which can be seeded by
4 another true random number generator.
7 - compatible : should be "microchip,pic32mzda-rng"
8 - reg : Specifies base physical address and size of the registers.
9 - clocks: clock phandle.
14 compatible = "microchip,pic32mzda-rng";
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| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | adi,axi-pwmgen.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI PWM generator
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 The Analog Devices AXI PWM generator can generate PWM signals
20 - $ref: pwm.yaml#
24 const: adi,axi-pwmgen-2.00.a
[all …]
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| /linux/arch/m68k/atari/ |
| H A D | atasound.c | 7 * unknown. (++roman: That's me... :-)
13 * 1998-05-31 ++andreas: atari_mksound rewritten to always use the envelope,
42 /* Busy wait for data being completely sent :-( */ in atari_microwire_cmd()
56 /* Generates sound of some frequency for some number of clock in atari_mksound()
65 /* Disable generator A in mixer control. */ in atari_mksound()
79 /* Set generator A frequency to hz. */ in atari_mksound()
93 /* Envelope form: max -> min single. */ in atari_mksound()
96 /* Use envelope for generator A. */ in atari_mksound()
100 /* Set generator A level to maximum, no envelope. */ in atari_mksound()
104 /* Turn on generator A in mixer control. */ in atari_mksound()
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| /linux/include/linux/platform_data/ |
| H A D | ad7793.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
12 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
13 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
14 * @AD7793_CLK_SRC_EXT: Use external clock.
15 * @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
26 * @AD7793_BIAS_VOLTAGE_DISABLED: Bias voltage generator disabled
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
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| /linux/Documentation/devicetree/bindings/crypto/ |
| H A D | samsung-sss.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 -- Feeder (FeedCtrl)
15 -- Advanced Encryption Standard (AES)
16 -- Data Encryption Standard (DES)/3DES
17 -- Public Key Accelerator (PKA)
18 -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
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| /linux/drivers/pwm/ |
| H A D | pwm-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
63 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
65 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
72 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
74 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
86 * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
88 * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
100 unsigned int channel = pwm->hwpwm; in brcmstb_pwm_config()
[all …]
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