/linux/sound/pci/lola/ |
H A D | lola_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Support for Digigram Lola PCI-e boards 17 unsigned int freq; in lola_sample_rate_convert() local 21 case 0: freq = 48000; break; in lola_sample_rate_convert() 22 case 1: freq = 44100; break; in lola_sample_rate_convert() 23 case 2: freq in lola_sample_rate_convert() 57 check_gran_clock_compatibility(struct lola * chip,unsigned int val,unsigned int freq) check_gran_clock_compatibility() argument 159 unsigned int freq = items[j] & 0xff; lola_init_clock_widget() local 262 int freq = 0; lola_set_clock() local [all...] |
/linux/sound/drivers/vx/ |
H A D | vx_uer.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 17 * vx_modify_board_clock - tell the board that its clock has been modified 32 * vx_modify_board_inputs - resync audio inputs 44 * vx_read_one_cbit - read one bit from UER config 52 mutex_lock(&chip->lock); in vx_read_one_cbit() 53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit() 62 mutex_unlock(&chip->lock); in vx_read_one_cbit() 67 * vx_write_one_cbit - write one bit to UER config 74 mutex_lock(&chip->lock); in vx_write_one_cbit() 82 mutex_unlock(&chip->lock); in vx_write_one_cbit() [all …]
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/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Brian Norris <briannorris@chromium.org> 15 - rockchip,rk3399-dmc 17 devfreq-events: 26 clock-names: 28 - const: dmc_clk 30 operating-points-v2: true [all …]
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/linux/drivers/net/can/mscan/ |
H A D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>, 7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> 40 { .compatible = "fsl,mpc5200-cdm", }, 50 unsigned int freq; in mpc52xx_can_get_clock() local 56 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock() 57 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock() 58 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock() 68 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock() 69 if (!freq) in mpc52xx_can_get_clock() [all …]
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/linux/drivers/clocksource/ |
H A D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 34 if (priv->big_endian) in ftm_readl() 42 if (priv->big_endian) in ftm_writel() 52 /* select and enable counter clock source */ in ftm_counter_enable() 55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable() 63 /* disable counter clock source */ in ftm_counter_disable() 108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock() 119 * a, the counter source clock is disabled. in ftm_set_next_event() 121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event() 124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event() [all …]
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_afmt.c | 34 /* Clock N CTS N CTS N CTS */ 51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument 57 n = 128 * freq; in amdgpu_afmt_calc_cts() 58 cts = clock * 1000; in amdgpu_afmt_calc_cts() 67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts() 70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts() 76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts() 78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts() 85 *N, *CTS, freq); in amdgpu_afmt_calc_cts() 88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument [all …]
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/linux/drivers/sh/clk/ |
H A D | core.c | 2 * SuperH clock framework 4 * Copyright (C) 2005 - 2010 Paul Mundt 6 * This clock framework is derived from the OMAP version by: 8 * Copyright (C) 2004 - 2008 Nokia Corporation 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 17 #define pr_fmt(fmt) "clock: " fmt 36 /* clock disable operations are not passed on to hardware during boot */ 46 unsigned long freq; in clk_rate_table_build() local 49 clk->nr_freqs = nr_freqs; in clk_rate_table_build() 55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build() [all …]
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | ufs-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alim Akhtar <alim.akhtar@samsung.com> 11 - Avri Altman <avri.altman@wdc.com> 16 clock-names: true 18 freq-table-hz: 21 - description: Minimum frequency for given clock in Hz 22 - description: Maximum frequency for given clock in Hz [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | atmel,sama5d2-pdmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 20 const: atmel,sama5d2-pdmic 30 - description: peripheral clock 31 - description: generated clock 33 clock-names: 35 - const: pclk [all …]
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/linux/drivers/clk/ti/ |
H A D | fapll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 #include <linux/clk-provider.h> 13 #include "clock.h" 43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 73 void __iomem *freq; member 81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass() 83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass() 91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass() 93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass() 97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass() [all …]
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/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca5s.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A5 MPCore (V2P-CA5s) 8 * HBI-0225B 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA5s"; 18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <1>; 21 #size-cells = <1>; [all …]
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H A D | vexpress-v2p-ca15-tc1.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A15 MPCore (V2P-CA15) 8 * HBI-0237A 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA15"; 18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; [all …]
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H A D | vexpress-v2p-ca15_a7.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Cortex-A15_A7 MPCore (V2P-CA15_A7) 8 * HBI-0249A 11 /dts-v1/; 12 #include "vexpress-v2m-rs1.dtsi" 15 model = "V2P-CA15_CA7"; 18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; [all …]
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/linux/drivers/cpufreq/ |
H A D | armada-8k-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0+ 25 { .compatible = "marvell,ap806-cpu-clock" }, 26 { .compatible = "marvell,ap807-cpu-clock" }, 41 unsigned int freq[ARRAY_SIZE(opps_div)]; member 44 /* If the CPUs share the same clock, then they are in the same cluster. */ 62 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus() 77 unsigned int freq; in armada_8k_add_opp() local 83 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp() 84 return -EINVAL; in armada_8k_add_opp() 90 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp() [all …]
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/linux/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_clock_utils.c | 1 // SPDX-License-Identifier: MIT 60 u32 freq = 0; in gen11_read_clock_frequency() local 63 * Note that on gen11+, the clock frequency may be reconfigured. in gen11_read_clock_frequency() 72 freq = read_reference_ts_freq(uncore); in gen11_read_clock_frequency() 76 freq = gen11_get_crystal_clock_freq(uncore, c0); in gen11_read_clock_frequency() 81 * increment only every few clock cycle). in gen11_read_clock_frequency() 83 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency() 87 return freq; in gen11_read_clock_frequency() 93 u32 freq = 0; in gen9_read_clock_frequency() local 96 freq = read_reference_ts_freq(uncore); in gen9_read_clock_frequency() [all …]
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/linux/drivers/net/can/cc770/ |
H A D | cc770_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 * in your board-specific code: 29 * interrupt-parent = <&mpic>; 30 * bosch,external-clock-frequency = <16000000>; 53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus"); 61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg() 67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg() 74 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data() 76 of_property_read_u32(np, "bosch,external-clock-frequency", &clkext); in cc770_get_of_node_data() 77 priv->can.clock.freq = clkext; in cc770_get_of_node_data() [all …]
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/linux/drivers/clk/hisilicon/ |
H A D | clk-hi6220-stub.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Hi6220 stub clock driver 11 #include <linux/clk-provider.h> 69 unsigned int freq; in hi6220_acpu_get_freq() local 71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq() 72 return freq; in hi6220_acpu_get_freq() 76 unsigned int freq) in hi6220_acpu_set_freq() argument 81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq() 89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq() 94 unsigned int freq) in hi6220_acpu_round_freq() argument [all …]
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/linux/arch/mips/kernel/ |
H A D | time.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 24 #include <asm/cpu-features.h> 25 #include <asm/cpu-type.h> 39 struct cpufreq_freqs *freq = data; in cpufreq_callback() local 40 struct cpumask *cpus = freq->policy->cpus; in cpufreq_callback() 45 * Skip lpj numbers adjustment if the CPU-freq transition is safe for in cpufreq_callback() 48 if (freq->flags & CPUFREQ_CONST_LOOPS) in cpufreq_callback() 54 glb_lpj_ref_freq = freq->old; in cpufreq_callback() 59 per_cpu(pcp_lpj_ref_freq, cpu) = freq->old; in cpufreq_callback() 64 * Adjust global lpj variable and per-CPU udelay_val number in in cpufreq_callback() [all …]
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/linux/drivers/devfreq/ |
H A D | imx8m-ddrc.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/clk-provider.h> 14 #include <linux/arm-smccc.h> 40 * +----------+ |\ +------+ 41 * | dram_pll |-------|M| dram_core | | 42 * +----------+ |U|---------->| D | 43 * /--|X| | D | 46 * +---------+ | | 48 * +---------+ | | 50 * +----------+ | | | [all …]
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/linux/include/linux/ |
H A D | clocksource.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 36 * struct clocksource - hardware abstraction for a free running counter 37 * Provides mostly state-free accessors to the underlying hardware. 49 * @archdata: Optional arch-specific data 60 * 1-99: Unfit for real use 62 * 100-199: Base level usability. 64 * 200-299: Good. 66 * 300-399: Desired. 68 * 400-499: Perfect 69 * The ideal clocksource. A must-use where [all …]
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/linux/arch/arm/mach-sa1100/include/mach/ |
H A D | SA-1100.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * FILE SA-1100.h 9 * System StrongARM SA-1100 12 * SA-1100 microprocessor (Advanced RISC Machine (ARM) 14 * StrongARM SA-1100 data sheet version 2.2. 21 #error You must include hardware.h not SA-1100.h 91 * Controller (UDC) Control/Status register end-point 0 94 * Controller (UDC) Control/Status register end-point 1 97 * Controller (UDC) Control/Status register end-point 2 100 * Controller (UDC) Data register end-point 0 [all …]
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/linux/drivers/accel/amdxdna/ |
H A D | aie2_smu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 42 XDNA_ERR(ndev->xdna, "smu cmd %d timed out", reg_cmd); in aie2_smu_exec() 50 XDNA_ERR(ndev->xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp); in aie2_smu_exec() 51 return -EINVAL; in aie2_smu_exec() 59 u32 freq; in npu1_set_dpm() local 63 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq); in npu1_set_dpm() 65 XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n", in npu1_set_dpm() 66 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret); in npu1_set_dpm() 68 ndev->npuclk_freq = freq; in npu1_set_dpm() [all …]
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/linux/kernel/time/ |
H A D | clockevents.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * This file contains functions which manage clock event devices. 5 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar 7 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner 17 #include "tick-internal.h" 19 /* The registered clock event devices */ 35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns() 38 if (WARN_ON(!evt->mult)) in cev_delta2ns() 39 evt->mult = 1; in cev_delta2ns() [all …]
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/linux/arch/x86/kernel/ |
H A D | tsc_msr.c | 1 // SPDX-License-Identifier: GPL-2.0 14 #include <asm/intel-family.h> 23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs 26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or 30 * So we can create a simplified model of the CPU clock setup using a reference 31 * clock of 100 MHz plus a quotient which gets us as close to the frequency 62 * Penwell and Clovertrail use spread spectrum clock, 63 * so the freq number is not exactly the same as reported 161 * MSR-based CPU/TSC frequency discovery for certain CPUs. 168 u32 lo, hi, ratio, freq, tscref; in cpu_khz_from_msr() local [all …]
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/linux/sound/soc/fsl/ |
H A D | fsl_esai.c | 1 // SPDX-License-Identifier: GPL-2.0 17 #include "imx-pcm.h" 25 * struct fsl_esai_soc_data - soc specific data 33 * struct fsl_esai - ESAI private data 38 * @coreclk: clock source to access register 39 * @extalclk: esai clock source to derive HCK, SCK and FS 40 * @fsysclk: system clock source to derive HCK, SCK and FS 41 * @spbaclk: SPBA clock (optional, depending on SoC design) 51 * @hck_rate: clock rate of desired HCKx clock 52 * @sck_rate: clock rate of desired SCKx clock [all …]
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