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/linux/sound/drivers/vx/
H A Dvx_uer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 guard(mutex)(&chip->loc in vx_read_one_cbit()
94 int val, freq; vx_read_uer_status() local
148 vx_calc_clock_from_freq(struct vx_core * chip,int freq) vx_calc_clock_from_freq() argument
193 vx_set_internal_clock(struct vx_core * chip,unsigned int freq) vx_set_internal_clock() argument
195 int clock; vx_set_internal_clock() local
232 vx_set_clock(struct vx_core * chip,unsigned int freq) vx_set_clock() argument
276 int freq; vx_change_frequency() local
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
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/linux/drivers/net/can/mscan/
H A Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
40 { .compatible = "fsl,mpc5200-cdm", },
50 unsigned int freq; in mpc52xx_can_get_clock() local
56 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
57 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
58 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
68 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
69 if (!freq) in mpc52xx_can_get_clock()
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/linux/drivers/clocksource/
H A Dtimer-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is disabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
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H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
41 #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
50 #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c34 /* Clock N CTS N CTS N CTS */
51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
57 n = 128 * freq; in amdgpu_afmt_calc_cts()
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts()
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts()
78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
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/linux/drivers/sh/clk/
H A Dcore.c2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
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/linux/Documentation/devicetree/bindings/sound/
H A Datmel,sama5d2-pdmic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
20 const: atmel,sama5d2-pdmic
30 - description: peripheral clock
31 - description: generated clock
33 clock-names:
35 - const: pclk
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/linux/drivers/clk/ti/
H A Dfapll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
13 #include "clock.h"
43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
73 void __iomem *freq; member
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass()
97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux/drivers/cpufreq/
H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
25 { .compatible = "marvell,ap806-cpu-clock" },
26 { .compatible = "marvell,ap807-cpu-clock" },
41 unsigned int freq[ARRAY_SIZE(opps_div)]; member
44 /* If the CPUs share the same clock, then they are in the same cluster. */
62 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus()
77 unsigned int freq; in armada_8k_add_opp() local
83 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp()
84 return -EINVAL; in armada_8k_add_opp()
90 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp()
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/linux/drivers/net/can/cc770/
H A Dcc770_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * in your board-specific code:
29 * interrupt-parent = <&mpic>;
30 * bosch,external-clock-frequency = <16000000>;
53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus");
61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
74 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data()
76 of_property_read_u32(np, "bosch,external-clock-frequency", &clkext); in cc770_get_of_node_data()
77 priv->can.clock.freq = clkext; in cc770_get_of_node_data()
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/linux/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hi6220 stub clock driver
11 #include <linux/clk-provider.h>
69 unsigned int freq; in hi6220_acpu_get_freq() local
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
72 return freq; in hi6220_acpu_get_freq()
76 unsigned int freq) in hi6220_acpu_set_freq() argument
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
94 unsigned int freq) in hi6220_acpu_round_freq() argument
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/linux/arch/mips/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <asm/cpu-features.h>
25 #include <asm/cpu-type.h>
39 struct cpufreq_freqs *freq = data; in cpufreq_callback() local
40 struct cpumask *cpus = freq->policy->cpus; in cpufreq_callback()
45 * Skip lpj numbers adjustment if the CPU-freq transition is safe for in cpufreq_callback()
48 if (freq->flags & CPUFREQ_CONST_LOOPS) in cpufreq_callback()
54 glb_lpj_ref_freq = freq->old; in cpufreq_callback()
59 per_cpu(pcp_lpj_ref_freq, cpu) = freq->old; in cpufreq_callback()
64 * Adjust global lpj variable and per-CPU udelay_val number in in cpufreq_callback()
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/linux/drivers/devfreq/
H A Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
50 * +----------+ | | |
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
68 * 400-499: Perfect
69 * The ideal clocksource. A must-use where
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/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
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/linux/kernel/time/
H A Dclockevents.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains functions which manage clock event devices.
5 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
7 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner
17 #include "tick-internal.h"
19 /* The registered clock event devices */
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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/linux/drivers/leds/blink/
H A Dleds-lgm-sso.c1 // SPDX-License-Identifier: GPL-2.0
23 #define SSO_DEV_NAME "lgm-sso"
37 #define SSO_CON1_FCDSC GENMASK(21, 20) /* Fixed Divider Shift Clock */
55 #define DATA_CLK_EDGE 0 /* 0-rising, 1-falling */
63 * SW - Software has to update the SWU bit
64 * GPTC - General Purpose timer is used as clock source
65 * FPID - Divided FSC clock (FPID) is used as clock source
127 int freq; member
139 u32 freq[MAX_FREQ_RANK]; member
149 if (rate <= priv->freq[i]) in sso_get_blink_rate_idx()
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/linux/drivers/net/can/rockchip/
H A Drockchip_canfd-timestamp.c1 // SPDX-License-Identifier: GPL-2.0
4 // Marc Kleine-Budde <kernel@pengutronix.de>
24 ns = timecounter_cyc2time(&priv->tc, timestamp); in rkcanfd_skb_set_timestamp()
26 hwtstamps->hwtstamp = ns_to_ktime(ns); in rkcanfd_skb_set_timestamp()
35 timecounter_read(&priv->tc); in rkcanfd_timestamp_work()
37 schedule_delayed_work(&priv->timestamp, priv->work_delay_jiffies); in rkcanfd_timestamp_work()
42 const struct can_bittiming *dbt = &priv->can.fd.data_bittiming; in rkcanfd_timestamp_init()
43 const struct can_bittiming *bt = &priv->can.bittiming; in rkcanfd_timestamp_init()
44 struct cyclecounter *cc = &priv->cc; in rkcanfd_timestamp_init()
49 /* At the standard clock rate of 300Mhz on the rk3658, the 32 in rkcanfd_timestamp_init()
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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