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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
H A Datmel,sama5d2-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
15 - atmel,sama5d2-adc
16 - microchip,sam9x60-adc
17 - microchip,sama7g5-adc
28 clock-names:
31 vref-supply: true
[all …]
/linux/drivers/spi/
H A Dspi-bitbang-txrx.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * simple SPI master driver. Two do polled word-at-a-time I/O:
6 * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
7 * expanding the per-word routines from the inline templates below.
9 * - Drivers for controllers resembling bare shift registers. Provide
11 * that use your controller's clock and chipselect registers.
15 * - Drivers leveraging smarter hardware, with fifos or DMA; or for half
36 * A non-inlined routine would call bitbang_txrx_*() routines. The
43 * particular CPU clock rate.
55 u32 oldbit = (!(word & (1<<(bits-1)))) << 31; in bitbang_txrx_be_cpha0()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
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/linux/Documentation/userspace-api/gpio/
H A Dgpio-lineevent-data-read.rst1 .. SPDX-License-Identifier: GPL-2.0
11 gpio-v2-line-event-read.rst.
16 GPIO_LINEEVENT_DATA_READ - Read edge detection events from a line event.
28 :c:type:`request.fd<gpioevent_request>` by gpio-get-lineevent-ioctl.rst.
40 Read edge detection events for a line from a line event.
42 Edge detection must be enabled for the input line using either
44 both. Edge events are then generated whenever edge interrupts are detected on
48 to active transition is a rising edge. If ``GPIOHANDLE_REQUEST_ACTIVE_LOW`` is
50 ``GPIOEVENT_REQUEST_RISING_EDGE`` then corresponds to a falling physical edge.
52 The kernel captures and timestamps edge events as close as possible to their
[all …]
H A Dgpio-v2-get-line-ioctl.rst1 .. SPDX-License-Identifier: GPL-2.0
12 GPIO_V2_GET_LINE_IOCTL - Request a line or lines from the kernel.
37 :ref:`gpio-v2-line-request`.
41 as possible. e.g. gpio-v2-line-get-values-ioctl.rst will read all the
53 .. _gpio-v2-get-line-config-rules:
56 -------------------
63 and the line is requested "as-is" to allow reading of the line value
69 If none are set then the line is assumed push-pull.
75 The edge flags, ``GPIO_V2_LINE_FLAG_EDGE_xxx``, require
77 and falling edges. Requesting edge detection from a line that does not support
[all …]
/linux/drivers/media/dvb-frontends/
H A Dm88ds3103.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * enum m88ds3103_ts_mode - TS connection mode
34 * @M88DS3103_CLOCK_OUT_DISABLED: Clock output is disabled
35 * @M88DS3103_CLOCK_OUT_ENABLED: Clock output is enabled with crystal
36 * clock.
37 * @M88DS3103_CLOCK_OUT_ENABLED_DIV2: Clock output is enabled with half
38 * crystal clock.
47 * struct m88ds3103_platform_data - Platform data for the m88ds3103 driver
48 * @clk: Clock frequency.
51 * @ts_clk: TS clock (KHz).
[all …]
/linux/Documentation/sound/soc/
H A Ddai.rst15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
53 receive the audio data. Bit clock usually varies depending on sample rate
58 Common PCM operating modes:-
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-adsp-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,sc7280-adsp-pil
23 - description: qdsp6ss register
24 - description: efuse q6ss register
28 - description: Phandle to apps_smmu node with sid mask
32 - description: Watchdog interrupt
[all …]
H A Dqcom,q6v5.txt6 - compatible:
10 "qcom,ipq8074-wcss-pil"
11 "qcom,qcs404-wcss-pil"
13 - reg:
15 Value type: <prop-encoded-array>
19 - reg-names:
24 - interrupts-extended:
26 Value type: <prop-encoded-array>
27 Definition: reference to the interrupts that match interrupt-names
29 - interrupt-names:
[all …]
/linux/arch/arm/boot/dts/st/
H A Dst-pincfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 /* User-frendly defines for Pin Direction */
49 * single-edge data non inverted clock, retime data with clk
54 * single-edge data inverted clock, retime data with clk
59 * double-edge data, retime data with clk
63 * CIV0, CIV1 modes with inverted clock
64 * Retiming the clk pins will park clock & reduce the noise within the core.
68 * CLK0, CLK1 modes with non-inverted clock
69 * Retiming the clk pins will park clock & reduce the noise within the core.
/linux/drivers/pinctrl/
H A Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
40 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
41 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dmicrochip,sama7g5-pdmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/microchip,sama7g5-pdmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
17 - $ref: dai-common.yaml#
21 const: microchip,sama7g5-pdmc
26 "#sound-dai-cells":
34 - description: Peripheral Bus Clock
35 - description: Generic Clock
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,smd-rpm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 The SMD or GLINK information for the RPM edge should be filled out. See
16 qcom,smd.yaml for the required edge properties. All SMD/GLINK related
23 Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
28 - Andy Gross <agross@kernel.org>
29 - Bjorn Andersson <bjorn.andersson@linaro.org>
34 - items:
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
/linux/include/linux/
H A Dhte.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * enum hte_edge - HTE line edge flags.
15 * @HTE_EDGE_NO_SETUP: No edge setup. In this case consumer will setup edges,
17 * @HTE_RISING_EDGE_TS: Rising edge.
18 * @HTE_FALLING_EDGE_TS: Falling edge.
28 * enum hte_return - HTE subsystem return values used during callback.
41 * struct hte_ts_data - HTE timestamp data.
46 * -1 otherwise.
55 * struct hte_clk_info - Clock source info that HTE provider uses to timestamp.
57 * @hz: Supported clock rate in HZ, for example 1KHz clock = 1000.
[all …]
/linux/sound/pci/ice1712/
H A Ddelta.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Lowlevel functions for M-Audio Delta 1010, 44, 66, Dio2496, Audiophile
44 * MidiMan M-Audio Delta GPIO definitions
47 /* MidiMan M-Audio Delta shared pins */
56 /* S/PDIF output status clock */
57 /* (writing on rising edge - 0->1) */
64 /* MidiMan M-Audio DeltaDiO */
73 /* MidiMan M-Audio Delta1010 */
79 /* 1 - clock are taken from S/PDIF input */
80 /* 0 - clock are taken from Word Clock input */
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5755.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
[all …]
/linux/drivers/pwm/
H A Dpwm-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
27 #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
60 * either edge or neither egde.
123 clk_rate = clk_get_rate(pc->pwm_clk); in sti_pwm_get_prescale()
125 dev_err(pc->dev, "failed to get clock rate\n"); in sti_pwm_get_prescale()
126 return -EINVAL; in sti_pwm_get_prescale()
130 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1 in sti_pwm_get_prescale()
133 value *= pc->max_pwm_cnt + 1; in sti_pwm_get_prescale()
[all …]
/linux/include/sound/
H A Dcs8427.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
68 #define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
72 #define CS8427_RUN (1<<6) /* 0 = clock off, 1 = clock on */
77 #define CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */
[all …]
/linux/include/soc/at91/
H A Datmel_tcb.h17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
30 * timers. Then they use clk_get() and platform_get_irq() to get clock and
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
50 * struct atmel_tc - information about a Timer/Counter Block
56 * @clk: internal clock source for each of the three channels
61 * while on others, all TC channels share the same clock and IRQ.
[all …]
/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -E val enable rising (1), falling (2), or both (3) edges\n" in usage()
124 " -f val adjust the ptp clock frequency by 'val' ppb\n" in usage()
125 " -F chan Enable single channel mask and keep device open for debugfs verification.\n" in usage()
[all …]

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