Home
last modified time | relevance | path

Searched +full:clock +full:- +full:bindings (Results 1 – 25 of 1116) sorted by relevance

12345678910>>...45

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8450-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM8450
10 - Konrad Dybcio <konradybcio@kernel.org>
11 - Taniya Das <taniya.das@oss.qualcomm.com>
14 Qualcomm graphics clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,glymur-gpucc.h
19 include/dt-bindings/clock/qcom,kaanapali-gpucc.h
[all …]
H A Dqcom,sm8450-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller on SM8450
10 - Taniya Das <taniya.das@oss.qualcomm.com>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
14 Qualcomm video clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,glymur-videocc.h
19 include/dt-bindings/clock/qcom,hawi-videocc.h
[all …]
H A Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 Qualcomm display clock control module provides the clocks, resets and power
18 - include/dt-bindings/clock/qcom,kaanapali-dispcc.h
19 - include/dt-bindings/clock/qcom,nord-dispcc.h
[all …]
H A Dqcom,sm8450-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on SM8450
10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
12 - Taniya Das <taniya.das@oss.qualcomm.com>
15 Qualcomm camera clock control module provides the clocks, resets and power
19 include/dt-bindings/clock/qcom,kaanapali-camcc.h
[all …]
H A Dqcom,sm8550-tcsr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Taniya Das <taniya.das@oss.qualcomm.com>
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,eliza-tcsr.h
19 - include/dt-bindings/clock/qcom,hawi-tcsrcc.h
[all …]
H A Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
6 This binding uses the following bindings:
7 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 Documentation/devicetree/bindings/reset/reset.txt
12 - compatible: should be one of the following.
13 - "hisilicon,hi3516cv300-crg"
14 - "hisilicon,hi3516cv300-sysctrl"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
[all …]
H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
[all …]
H A Dqcom,qcm2290-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on QCM2290
10 - Loic Poulain <loic.poulain@linaro.org>
13 Qualcomm display clock control module provides the clocks, resets and power
16 See also: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
21 - items:
22 - enum:
[all …]
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
[all …]
H A Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
16 Each clock is assigned an identifier and client nodes use this identifier
17 to specify the clock which they consume.
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
[all …]
H A Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
[all …]
H A Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
[all …]
H A Dqcom,x1e80100-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Clock & Reset Controller on x1e80100
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
11 - Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
14 Qualcomm camera clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,glymur-camcc.h
19 include/dt-bindings/clock/qcom,x1e80100-camcc.h
[all …]
H A Dqcom,dispcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm display clock control module which supports the clocks, resets and
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
[all …]
H A Dqcom,sa8775p-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SA8775P
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm display clock control module provides the clocks, resets and power
16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
21 - qcom,sa8775p-dispcc0
22 - qcom,sa8775p-dispcc1
[all …]
H A Drenesas,r9a08g045-vbattb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 controls the RTC clock (VBATTCLK), tamper detection logic and a small
15 - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
19 const: renesas,r9a08g045-vbattb
26 - description: tamper detector interrupt
30 - description: VBATTB module clock
31 - description: RTC input clock (crystal or external clock device)
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
[all …]
/linux/rust/kernel/
H A Dtime.rs1 // SPDX-License-Identifier: GPL-2.0
10 //! - The [`Instant`] type represents a specific point in time.
11 //! - The [`Delta`] type represents a span of time.
34 pub const NSEC_PER_USEC: i64 = bindings::NSEC_PER_USEC as i64;
37 pub const NSEC_PER_MSEC: i64 = bindings::NSEC_PER_MSEC as i64;
40 pub const NSEC_PER_SEC: i64 = bindings::NSEC_PER_SEC as i64;
50 pub fn msecs_to_jiffies(msecs: Msecs) -> Jiffies { in msecs_to_jiffies()
53 unsafe { bindings::__msecs_to_jiffies(msecs) } in msecs_to_jiffies()
56 /// Trait for clock sources.
58 /// Selection of the clock source depends on the use case. In some cases the usage of a
[all …]
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen.txt30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
30 figure out the chip-id.
[all …]
H A Dqcom,qcm2290-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
18 $ref: /schemas/display/msm/mdss-common.yaml#
23 - const: qcom,qcm2290-mdss
24 - items:
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 booting process handling and offloading the power management, clock
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
28 This node is a clock, power domain, and reset provider. See the
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Min Guo <min.guo@mediatek.com>
15 pattern: '^usb@[0-9a-f]+$'
19 - enum:
20 - mediatek,mt8516-musb
21 - mediatek,mt2701-musb
22 - mediatek,mt7623-musb
23 - const: mediatek,mtk-musb
[all …]

12345678910>>...45