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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Imran Shaik <quic_imrashai@quicinc.com>
14 Qualcomm graphics clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gpucc-sdm845.h
19 include/dt-bindings/clock/qcom,gpucc-sa8775p.h
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H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm video clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,sm6350-videocc.h
18 include/dt-bindings/clock/qcom,videocc-sc7180.h
19 include/dt-bindings/clock/qcom,videocc-sc7280.h
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H A Dqcom,sm8550-tcsr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm TCSR Clock Controller on SM8550
10 - Bjorn Andersson <andersson@kernel.org>
11 - Taniya Das <taniya.das@oss.qualcomm.com>
14 Qualcomm TCSR clock control module provides the clocks, resets and
18 - include/dt-bindings/clock/qcom,glymur-tcsr.h
19 - include/dt-bindings/clock/qcom,sm8550-tcsr.h
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H A Dhisi-crg.txt1 * HiSilicon Clock and Reset Generator(CRG)
3 The CRG module provides clock and reset signals to various
6 This binding uses the following bindings:
7 Documentation/devicetree/bindings/clock/clock-bindings.txt
8 Documentation/devicetree/bindings/reset/reset.txt
12 - compatible: should be one of the following.
13 - "hisilicon,hi3516cv300-crg"
14 - "hisilicon,hi3516cv300-sysctrl"
15 - "hisilicon,hi3519-crg"
16 - "hisilicon,hi3798cv200-crg"
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H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
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H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
10 - Jonathan Marek <jonathan@marek.ca>
13 Qualcomm display clock control module provides the clocks, resets and power
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
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H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
6 See clock_bindings.txt for more information on the generic clock bindings.
9 == Clock Controller ==
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
11 required input clock frequencies from the devicetree and acts as clock provider
12 for all clock consumers of PS clocks.
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
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H A Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
16 Each clock is assigned an identifier and client nodes use this identifier
17 to specify the clock which they consume.
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
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H A Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
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H A Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
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H A Dqcom,gcc-msm8916.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
14 Qualcomm global clock control module provides the clocks, resets and power
18 include/dt-bindings/clock/qcom,gcc-msm8916.h
19 include/dt-bindings/clock/qcom,gcc-msm8939.h
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H A Dqcom,dispcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SC8280XP
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm display clock control module which supports the clocks, resets and
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
22 - qcom,sc8280xp-dispcc0
23 - qcom,sc8280xp-dispcc1
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H A Dqcom,ipq9574-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
14 Qualcomm networking sub system clock control module provides the clocks,
18 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
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H A Dqcom,sa8775p-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SA8775P
10 - Taniya Das <quic_tdas@quicinc.com>
13 Qualcomm display clock control module provides the clocks, resets and power
16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
21 - qcom,sa8775p-dispcc0
22 - qcom,sa8775p-dispcc1
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/linux/rust/kernel/
H A Dtime.rs1 // SPDX-License-Identifier: GPL-2.0
10 //! - The [`Instant`] type represents a specific point in time.
11 //! - The [`Delta`] type represents a span of time.
34 pub const NSEC_PER_USEC: i64 = bindings::NSEC_PER_USEC as i64;
37 pub const NSEC_PER_MSEC: i64 = bindings::NSEC_PER_MSEC as i64;
40 pub const NSEC_PER_SEC: i64 = bindings::NSEC_PER_SEC as i64;
50 pub fn msecs_to_jiffies(msecs: Msecs) -> Jiffies { in msecs_to_jiffies()
53 unsafe { bindings in msecs_to_jiffies()
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
10 internally within the SoC or external components) two sets of bindings is needed:
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen.txt30 This binding uses the common clock binding[1].
33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
36 [7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
37 [8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt
41 - reg : A Base address and length of the register set.
45 clockgen-a@90ff000 {
46 compatible = "st,clkgen-c32";
49 clk_s_a0_pll: clk-s-a0-pll {
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
4 Documentation/devicetree/bindings/mmc/mmc.txt and the properties
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
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/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
21 - st,stm32mp15-i2c
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
22 '#address-cells':
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,qcm2290-mdss
25 - description: Display AHB clock from gcc
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/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 booting process handling and offloading the power management, clock
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
28 This node is a clock, power domain, and reset provider. See the
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/linux/Documentation/devicetree/bindings/serial/
H A Datmel,at91-usart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Richard Genoud <richard.genoud@bootlin.com>
16 - enum:
17 - atmel,at91rm9200-usart
18 - atmel,at91sam9260-usart
19 - items:
20 - const: atmel,at91rm9200-dbgu
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3036-usb2phy
17 - rockchip,rk3128-usb2phy
18 - rockchip,rk3228-usb2phy
19 - rockchip,rk3308-usb2phy
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