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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sx.dtsi84 clocks = <&clks IMX6SX_CLK_ARM>,
85 <&clks IMX6SX_CLK_PLL2_PFD2>,
86 <&clks IMX6SX_CLK_STEP>,
87 <&clks IMX6SX_CLK_PLL1_SW>,
88 <&clks IMX6SX_CLK_PLL1_SYS>;
170 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
179 clocks = <&clks IMX6SX_CLK_OCRAM>;
205 clocks = <&clks IMX6SX_CLK_GPU>,
206 <&clks IMX6SX_CLK_GPU>,
207 <&clks IMX6SX_CLK_GPU>;
[all …]
H A Dimx27.dtsi72 clocks = <&clks IMX27_CLK_CPU_DIV>;
95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 <&clks IMX27_CLK_DMA_AHB_GATE>;
106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 <&clks IMX27_CLK_PER1_GATE>;
122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 <&clks IMX27_CLK_PER1_GATE>;
131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 <&clks IMX27_CLK_PER1_GATE>;
[all …]
H A Dimx6ul.dtsi79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
176 clocks = <&clks IMX6UL_CLK_APBHDMA>;
187 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
188 <&clks IMX6UL_CLK_GPMI_APB>,
[all …]
H A Dimx6qdl.dtsi162 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
171 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
172 <&clks IMX6QDL_CLK_GPMI_APB>,
173 <&clks IMX6QDL_CLK_GPMI_BCH>,
174 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
175 <&clks IMX6QDL_CLK_PER1_BCH>;
187 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
188 <&clks IMX6QDL_CLK_HDMI_ISFR>;
218 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
219 <&clks IMX6QDL_CLK_GPU3D_CORE>,
[all …]
H A Dimx53.dtsi56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GAT
598 clks: ccm@53fd4000{ global() label
[all...]
H A Dimx25.dtsi105 clocks = <&clks 48>;
116 clocks = <&clks 48>;
126 clocks = <&clks 75>, <&clks 75>;
135 clocks = <&clks 76>, <&clks 76>;
144 clocks = <&clks 120>, <&clks 57>;
153 clocks = <&clks 121>, <&clks 5
347 clks: ccm@53f80000 { global() label
[all...]
H A Dimx7s.dtsi77 clocks = <&clks IMX7D_CLK_ARM>;
114 clocks = <&clks IMX7D_USB_PHY1_CLK>;
121 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
192 clocks = <&clks IMX7D_OCRAM_CLK>;
198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
229 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
244 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
279 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
302 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
[all …]
H A Dimx6sll.dtsi68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
162 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
163 <&clks IMX6SLL_CLK_OSC>,
164 <&clks IMX6SLL_CLK_SPDIF>,
165 <&clks IMX6SLL_CLK_DUMMY>,
166 <&clks IMX6SLL_CLK_DUMMY>,
[all …]
H A Dimx51.dtsi83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
138 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
148 clocks = <&clks IMX5_CLK_IPU_GATE>,
149 <&clks IMX5_CLK_IPU_DI0_GATE>,
150 <&clks IMX5_CLK_IPU_DI1_GATE>;
195 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
196 <&clks IMX5_CLK_DUMMY>,
197 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
206 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
[all …]
H A Dimx35.dtsi81 clocks = <&clks 51>;
92 clocks = <&clks 53>;
101 clocks = <&clks 9>, <&clks 70>;
110 clocks = <&clks 9>, <&clks 71>;
121 clocks = <&clks 52>;
132 clocks = <&clks 68>;
145 clocks = <&clks 35 &clks 35>;
155 clocks = <&clks 56>;
175 clocks = <&clks 9>, <&clks 72>;
187 clocks = <&clks 36 &clks 36>;
[all …]
H A Dimx50.dtsi91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 <&clks IMX5_CLK_DUMMY>,
124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 <&clks IMX5_CLK_DUMMY>,
136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 <&clks IMX5_CLK_UART3_PER_GATE>;
158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GAT
338 clks: ccm@53fd4000{ global() label
[all...]
H A Dimx6sl.dtsi70 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
71 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
72 <&clks IMX6SL_CLK_PLL1_SYS>;
121 clocks = <&clks IMX6SL_CLK_OCRAM>;
165 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
166 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
167 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
168 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
169 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
184 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
H A Dimx31.dtsi77 clocks = <&clks 33>;
87 clocks = <&clks 35>;
97 clocks = <&clks 26>;
105 clocks = <&clks 10>, <&clks 30>;
114 clocks = <&clks 10>, <&clks 31>;
123 clocks = <&clks 34>;
133 clocks = <&clks 10>, <&clks 53>;
146 clocks = <&clks 46>;
153 clocks = <&clks 10>, <&clks 49>;
163 clocks = <&clks 10>, <&clks 50>;
[all …]
H A Dimx6qp.dtsi15 clocks = <&clks IMX6QDL_CLK_OCRAM>;
24 clocks = <&clks IMX6QDL_CLK_OCRAM>;
32 clocks = <&clks IMX6QDL_CLK_PRE0>;
41 clocks = <&clks IMX6QDL_CLK_PRE1>;
50 clocks = <&clks IMX6QDL_CLK_PRE2>;
59 clocks = <&clks IMX6QDL_CLK_PRE3>;
67 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
68 <&clks IMX6QDL_CLK_PRG0_AXI>;
76 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
77 <&clks IMX6QDL_CLK_PRG1_AXI>;
[all …]
H A Dimx6q.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
H A Dimx1.dtsi51 clocks = <&clks IMX1_CLK_MCU>;
82 clocks = <&clks IMX1_CLK_HCLK>,
83 <&clks IMX1_CLK_PER1>;
91 clocks = <&clks IMX1_CLK_HCLK>,
92 <&clks IMX1_CLK_PER1>;
100 clocks = <&clks IMX1_CLK_DUMMY>,
101 <&clks IMX1_CLK_DUMMY>,
102 <&clks IMX1_CLK_PER2>;
111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clks IMX1_CLK_PER1>;
[all …]
H A Dimxrt1050.dtsi35 clocks = <&clks IMXRT1050_CLK_LPUART1>;
51 clks: clock-controller@400fc000 { label
58 assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
59 <&clks IMXRT1050_CLK_PLL1_BYPASS>,
60 <&clks IMXRT1050_CLK_PLL2_BYPASS>,
61 <&clks IMXRT1050_CLK_PLL3_BYPASS>,
62 <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
63 <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
64 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
65 <&clks IMXRT1050_CLK_PLL1_ARM>,
[all …]
H A Dimx7d.dtsi76 clocks = <&clks IMX7D_USB_PHY2_CLK>;
93 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
142 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
143 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
145 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
146 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
147 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
148 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
174 clocks = <&clks IMX7D_PXP_CL
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvfxxx.dtsi93 clocks = <&clks VF610_CLK_DMAMUX0>,
94 <&clks VF610_CLK_DMAMUX1>;
102 clocks = <&clks VF610_CLK_FLEXCAN0>,
103 <&clks VF610_CLK_FLEXCAN0>;
112 clocks = <&clks VF610_CLK_UART0>;
123 clocks = <&clks VF610_CLK_UART1>;
134 clocks = <&clks VF610_CLK_UART2>;
145 clocks = <&clks VF610_CLK_UART3>;
158 clocks = <&clks VF610_CLK_DSPI0>;
172 clocks = <&clks VF610_CLK_DSPI
435 clks: ccm@4006b000 { global() label
[all...]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc5121.dtsi50 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MBX>;
67 clocks = <&clks MPC512x_CLK_NFC>;
134 clks: clock@f00 { label
159 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512x_CLK_MSCAN0_MCL
[all...]
H A Dmpc5125twr.dts99 clks: clock@f00 { // Clock control label
129 clocks = <&clks MPC512x_CLK_BDLC>,
130 <&clks MPC512x_CLK_IPS>,
131 <&clks MPC512x_CLK_SYS>,
132 <&clks MPC512x_CLK_REF>,
133 <&clks MPC512x_CLK_MSCAN0_MCLK>;
141 clocks = <&clks MPC512x_CLK_BDLC>,
142 <&clks MPC512x_CLK_IPS>,
143 <&clks MPC512x_CLK_SYS>,
144 <&clks MPC512x_CLK_RE
[all...]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,asrc.txt64 clocks = <&clks 107>, <&clks 107>, <&clks 0>,
65 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
66 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
67 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
68 <&clks 107>, <&clks 0>, <&clks 0>;
H A Dfsl,imx-asrc.yaml158 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
159 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
160 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
161 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
162 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
163 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
164 <&clks IMX6QDL_CLK_SPBA>;
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa27x.dtsi38 clocks = <&clks CLK_NONE>;
45 clocks = <&clks CLK_USBHOST>;
53 clocks = <&clks CLK_PWM0>;
60 clocks = <&clks CLK_PWM1>;
67 clocks = <&clks CLK_PWM0>;
74 clocks = <&clks CLK_PWM1>;
81 clocks = <&clks CLK_PWRI2C>;
91 clocks = <&clks CLK_USB>;
99 clocks = <&clks CLK_KEYPAD>;
112 clocks = <&clks CLK_CAMERA>;
[all …]
/freebsd/sys/dev/fdt/
H A Dfdt_clock.c54 uint32_t *clks; in enable_disable_all() local
58 ncells = OF_getencprop_alloc_multi(cnode, "clocks", sizeof(*clks), in enable_disable_all()
59 (void **)&clks); in enable_disable_all()
67 clockdev = OF_device_from_xref(clks[i]); in enable_disable_all()
68 clocknum = clks[i + 1]; in enable_disable_all()
89 OF_prop_free(clks); in enable_disable_all()
99 uint32_t *clks; in fdt_clock_get_info() local
102 ncells = OF_getencprop_alloc_multi(cnode, "clocks", sizeof(*clks), in fdt_clock_get_info()
103 (void **)&clks); in fdt_clock_get_info()
110 clockdev = OF_device_from_xref(clks[n]); in fdt_clock_get_info()
[all …]

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