Lines Matching full:clks
35 clocks = <&clks IMXRT1050_CLK_LPUART1>;
51 clks: clock-controller@400fc000 { label
58 assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
59 <&clks IMXRT1050_CLK_PLL1_BYPASS>,
60 <&clks IMXRT1050_CLK_PLL2_BYPASS>,
61 <&clks IMXRT1050_CLK_PLL3_BYPASS>,
62 <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
63 <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
64 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
65 <&clks IMXRT1050_CLK_PLL1_ARM>,
66 <&clks IMXRT1050_CLK_PLL2_SYS>,
67 <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
68 <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
69 <&clks IMXRT1050_CLK_PLL2_SYS>;
81 clocks = <&clks IMXRT1050_CLK_DMA>,
82 <&clks IMXRT1050_CLK_DMA_MUX>;
89 clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
90 <&clks IMXRT1050_CLK_OSC>,
91 <&clks IMXRT1050_CLK_USDHC1>;