| /linux/drivers/clk/imx/ |
| H A D | clk-imx8mp-audiomix.c | 98 #define CLK_GATE(gname, cname) \ macro
180 CLK_GATE("asrc", ASRC_IPG),
181 CLK_GATE("pdm", PDM_IPG),
182 CLK_GATE("earc", EARC_IPG),
183 CLK_GATE("ocrama", OCRAMA_IPG),
184 CLK_GATE("aud2htx", AUD2HTX_IPG),
186 CLK_GATE("sdma2", SDMA2_ROOT),
187 CLK_GATE("sdma3", SDMA3_ROOT),
188 CLK_GATE("spba2", SPBA2_ROOT),
189 CLK_GATE("dsp", DSP_ROOT),
[all …]
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| H A D | clk-imx95-blk-ctl.c | 25 CLK_GATE, enumerator
67 .type = CLK_GATE,
77 .type = CLK_GATE,
87 .type = CLK_GATE,
107 .type = CLK_GATE,
117 .type = CLK_GATE,
127 .type = CLK_GATE,
137 .type = CLK_GATE,
147 .type = CLK_GATE,
177 .type = CLK_GATE,
[all …]
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| H A D | clk-gate-exclusive.c | 20 * The imx exclusive gate clock is a subclass of basic clk_gate
25 struct clk_gate gate;
31 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive()
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| H A D | clk-composite-7ulp.c | 30 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite()
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| H A D | clk-composite-93.c | 48 struct clk_gate *gate = to_clk_gate(hw); in imx93_clk_composite_gate_endisable()
198 struct clk_gate *gate = NULL; in imx93_clk_composite_flags()
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| H A D | clk-composite-8m.c | 209 struct clk_gate *gate = to_clk_gate(hw); in imx8m_clk_composite_gate_enable()
244 struct clk_gate *gate = NULL; in __imx8m_clk_hw_composite()
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| /linux/drivers/clk/socfpga/ |
| H A D | clk-gate-a10.c | 45 u32 clk_gate[2]; in __socfpga_gate_init() local
59 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in __socfpga_gate_init()
61 clk_gate[0] = 0; in __socfpga_gate_init()
63 if (clk_gate[0]) { in __socfpga_gate_init()
64 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; in __socfpga_gate_init()
65 socfpga_clk->hw.bit_idx = clk_gate[1]; in __socfpga_gate_init()
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| H A D | clk-gate.c | 139 u32 clk_gate[2]; in socfpga_gate_init() local
158 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in socfpga_gate_init()
160 clk_gate[0] = 0; in socfpga_gate_init()
162 if (clk_gate[0]) { in socfpga_gate_init()
163 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; in socfpga_gate_init()
164 socfpga_clk->hw.bit_idx = clk_gate[1]; in socfpga_gate_init()
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| H A D | clk.h | 40 struct clk_gate hw;
44 struct clk_gate hw;
56 struct clk_gate hw;
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| /linux/drivers/clk/ |
| H A D | clk-gate.c | 27 static inline u32 clk_gate_readl(struct clk_gate *gate) in clk_gate_readl()
35 static inline void clk_gate_writel(struct clk_gate *gate, u32 val) in clk_gate_writel()
58 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable()
106 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_is_enabled()
135 struct clk_gate *gate; in __clk_hw_register_gate()
163 /* struct clk_gate assignments */ in __clk_hw_register_gate()
202 struct clk_gate *gate; in clk_unregister_gate()
218 struct clk_gate *gate; in clk_hw_unregister_gate()
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| H A D | clk-loongson2.c | 98 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ macro
171 CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
172 CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
173 CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
174 CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
175 CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
176 CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
177 CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
178 CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
179 CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
[all …]
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| H A D | clk-aspeed.h | 34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
44 * This modified version of clk_gate allows an optional reset bit to be
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| H A D | clk-stm32f4.c | 514 struct clk_gate gate;
607 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_enable()
633 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_recalc()
645 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_round_rate()
662 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_set_rate()
909 struct clk_gate gate;
917 struct clk_gate *gate = to_clk_gate(hw); in rgclk_enable()
1059 struct clk_gate *gate; in stm32_register_cclk()
1630 struct clk_gate *gate = NULL; in stm32_register_aux_clk()
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| /linux/drivers/clk/ralink/ |
| H A D | clk-mt7621.c | 100 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_enable() local
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
109 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_disable() local
110 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable()
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
117 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_is_enabled() local
118 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_is_enabled()
124 return val & clk_gate->bit_idx; in mt7621_gate_is_enabled()
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| /linux/drivers/mmc/host/ |
| H A D | meson-mx-sdhc-clkc.c | 18 struct clk_gate mod_clk_en;
19 struct clk_gate tx_clk_en;
20 struct clk_gate rx_clk_en;
21 struct clk_gate sd_clk_en;
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-a10-hosc.c | 21 struct clk_gate *gate; in sun4i_osc_clk_setup()
32 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
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| H A D | clk-a20-gmac.c | 57 struct clk_gate *gate; in sun7i_a20_gmac_clk_setup()
70 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun7i_a20_gmac_clk_setup()
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| H A D | clk-a10-pll2.c | 45 struct clk_gate *gate; in sun4i_pll2_setup()
74 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_pll2_setup()
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| /linux/drivers/iio/adc/ |
| H A D | ad7625.c | 65 /* rate of the clock gated by the "clk_gate" PWM */
76 * properties for the clk_gate and cnv PWMs
187 * the duty_cycle for ref_clk, cnv, and clk_gate in ad7625_set_sampling_freq()
427 /* Disable cnv PWM if clk_gate setup failed */ in ad7625_buffer_preenable()
469 st->clk_gate_pwm = devm_pwm_get(dev, "clk_gate"); in devm_ad7625_pwm_get()
472 "failed to get clk_gate pwm\n"); in devm_ad7625_pwm_get()
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| /linux/drivers/clk/renesas/ |
| H A D | rcar-cpg-lib.c | 128 struct clk_gate gate;
178 struct clk_gate gate;
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| /linux/Documentation/driver-api/ |
| H A D | clk.rst | 111 struct clk_gate {
118 struct clk_gate contains struct clk_hw hw as well as hardware-specific
143 static void clk_gate_set_bit(struct clk_gate *gate)
154 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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| /linux/drivers/clk/mmp/ |
| H A D | clk-audio.c | 69 struct clk_gate sysclk_gate;
70 struct clk_gate sspa0_gate;
71 struct clk_gate sspa1_gate;
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| /linux/drivers/clk/st/ |
| H A D | clk-flexgen.c | 37 struct clk_gate pgate;
41 struct clk_gate fgate;
45 struct clk_gate sync;
51 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
162 struct clk_gate *config = to_clk_gate(sync_hw); in flexgen_set_rate()
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| /linux/drivers/clk/meson/ |
| H A D | vclk.h | 20 * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
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| /linux/drivers/clk/rockchip/ |
| H A D | clk.c | 50 struct clk_gate *gate = NULL; in rockchip_clk_register_branch()
128 struct clk_gate gate;
216 struct clk_gate *gate = NULL; in rockchip_clk_register_frac_branch()
321 struct clk_gate *gate = NULL; in rockchip_clk_register_factor_branch()
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