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Searched full:clk_gate (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/clk/
H A Dclk-loongson2.c109 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ macro
151 CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE, "clk_node_pll_gate", "clk_node_div", 0x00, 0),
152 CLK_GATE(LS2K0300_CLK_GMAC_GATE, "clk_gmac_gate", "clk_gmac_div", 0x00, 1),
153 CLK_GATE(LS2K0300_CLK_I2S_GATE, "clk_i2s_gate", "clk_i2s_div", 0x00, 2),
162 CLK_GATE(LS2K0300_CLK_NET_GATE, "clk_net_gate", "clk_net_div", 0x08, 1),
163 CLK_GATE(LS2K0300_CLK_DEV_GATE, "clk_dev_gate", "clk_dev_div", 0x08, 2),
169 CLK_GATE(LS2K0300_CLK_PIX_PLL_GATE, "clk_pix_pll_gate", "clk_pix_div", 0x10, 0),
170 CLK_GATE(LS2K0300_CLK_PIX_GATE, "clk_pix_gate", "clk_pix_scale", 0x24, 6),
171 CLK_GATE(LS2K0300_CLK_GMACBP_GATE, "clk_gmacbp_gate", "clk_gmacbp_div", 0x10, 1),
175 CLK_GATE(LS2K0300_CLK_USB_GATE, "clk_usb_gate", "clk_usb_scale", 0x24, 2),
[all …]
H A Dclk-aspeed.h34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
44 * This modified version of clk_gate allows an optional reset bit to be
H A Dclk-stm32f4.c542 struct clk_gate gate;
638 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_enable()
664 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_recalc()
678 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_determine_rate()
697 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_set_ssc()
723 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_set_rate()
853 struct clk_gate *gate = to_clk_gate(hw); in stm32f4_pll_init_ssc()
1052 struct clk_gate gate;
1060 struct clk_gate *gate = to_clk_gate(hw); in rgclk_enable()
1202 struct clk_gate *gate; in stm32_register_cclk()
[all …]
H A Dclk-fsl-sai.c25 struct clk_gate gate;
H A Dclk-stm32h7.c151 struct clk_gate gate;
162 struct clk_gate *gate = to_clk_gate(hw); in ready_gate_clk_enable()
190 struct clk_gate *gate = to_clk_gate(hw); in ready_gate_clk_disable()
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate()
335 struct clk_gate *gate; in _get_cgate()
365 struct clk_gate *gate = NULL; in get_cfg_composite_div()
/linux/drivers/clk/imx/
H A Dclk-imx95-blk-ctl.c26 CLK_GATE, enumerator
69 .type = CLK_GATE,
79 .type = CLK_GATE,
89 .type = CLK_GATE,
109 .type = CLK_GATE,
119 .type = CLK_GATE,
129 .type = CLK_GATE,
139 .type = CLK_GATE,
149 .type = CLK_GATE,
179 .type = CLK_GATE,
[all …]
H A Dclk-composite-7ulp.c30 struct clk_gate *gate = to_clk_gate(hw); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite()
/linux/drivers/clk/socfpga/
H A Dclk-gate-a10.c45 u32 clk_gate[2]; in __socfpga_gate_init() local
59 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in __socfpga_gate_init()
61 clk_gate[0] = 0; in __socfpga_gate_init()
63 if (clk_gate[0]) { in __socfpga_gate_init()
64 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; in __socfpga_gate_init()
65 socfpga_clk->hw.bit_idx = clk_gate[1]; in __socfpga_gate_init()
H A Dclk-gate.c139 u32 clk_gate[2]; in socfpga_gate_init() local
158 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); in socfpga_gate_init()
160 clk_gate[0] = 0; in socfpga_gate_init()
162 if (clk_gate[0]) { in socfpga_gate_init()
163 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; in socfpga_gate_init()
164 socfpga_clk->hw.bit_idx = clk_gate[1]; in socfpga_gate_init()
H A Dclk.h40 struct clk_gate hw;
44 struct clk_gate hw;
56 struct clk_gate hw;
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c100 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_enable() local
101 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_enable()
104 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
109 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_disable() local
110 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_disable()
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
117 struct mt7621_gate *clk_gate = to_mt7621_gate(hw); in mt7621_gate_is_enabled() local
118 struct regmap *sysc = clk_gate->priv->sysc; in mt7621_gate_is_enabled()
124 return val & clk_gate->bit_idx; in mt7621_gate_is_enabled()
/linux/drivers/clk/sunxi/
H A Dclk-a10-hosc.c21 struct clk_gate *gate; in sun4i_osc_clk_setup()
32 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
H A Dclk-a20-gmac.c57 struct clk_gate *gate; in sun7i_a20_gmac_clk_setup()
70 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun7i_a20_gmac_clk_setup()
H A Dclk-a10-pll2.c45 struct clk_gate *gate; in sun4i_pll2_setup()
74 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_pll2_setup()
H A Dclk-factors.h51 struct clk_gate *gate;
H A Dclk-a10-mod1.c25 struct clk_gate *gate; in sun4i_mod1_clk_setup()
H A Dclk-factors.c183 struct clk_gate *gate = NULL; in __sunxi_factors_register()
216 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in __sunxi_factors_register()
H A Dclk-sun4i-pll3.c25 struct clk_gate *gate; in sun4i_a10_pll3_setup()
/linux/drivers/clk/renesas/
H A Drcar-cpg-lib.c128 struct clk_gate gate;
178 struct clk_gate gate;
/linux/drivers/clk/st/
H A Dclk-flexgen.c37 struct clk_gate pgate;
41 struct clk_gate fgate;
45 struct clk_gate sync;
51 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
162 struct clk_gate *config = to_clk_gate(sync_hw); in flexgen_set_rate()
/linux/Documentation/driver-api/
H A Dclk.rst111 struct clk_gate {
118 struct clk_gate contains struct clk_hw hw as well as hardware-specific
143 static void clk_gate_set_bit(struct clk_gate *gate)
154 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
/linux/drivers/clk/mmp/
H A Dclk-audio.c69 struct clk_gate sysclk_gate;
70 struct clk_gate sspa0_gate;
71 struct clk_gate sspa1_gate;
/linux/drivers/clk/meson/
H A Dvclk.h20 * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
/linux/drivers/clk/rockchip/
H A Dclk.c51 struct clk_gate *gate = NULL; in rockchip_clk_register_branch()
129 struct clk_gate gate;
211 struct clk_gate *gate = NULL; in rockchip_clk_register_frac_branch()
316 struct clk_gate *gate = NULL; in rockchip_clk_register_factor_branch()
/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml40 "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":

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