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Searched +full:clk +full:- +full:mgr (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/fpga/
H A Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
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/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
20 - const: altr,clk-mgr
30 "#address-cells":
33 "#size-cells":
37 "^osc[0-9]$":
40 "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
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/linux/Documentation/devicetree/bindings/i2c/
H A Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
40 nuvoton,sys-mgr:
45 - compatible
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
152 struct clk *clkin;
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
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H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
21 #include <linux/clk.h>
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
100 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
147 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
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H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <linux/clk.h>
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
116 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
164 struct omap_overlay_manager *mgr = hdmi.output.manager; in hdmi_power_on_full() local
173 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
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H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk.h>
207 struct omap_overlay_manager *mgr);
209 struct omap_overlay_manager *mgr);
303 struct clk *dss_clk;
408 return to_platform_device(dssdev->dev); in dsi_get_dsidev_from_dssdev()
429 return out ? to_platform_device(out->dev) : NULL; in dsi_get_dsidev_from_id()
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux/drivers/clk/socfpga/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
14 #include "clk.h"
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
79 const char *clk_name = node->name; in __socfpga_pll_init()
91 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
34 /* functions shared with other clk mgr */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.h2 * Copyright 2012-16 Advanced Micro Devices, Inc.
37 /* functions shared with other clk mgr*/
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c1 // SPDX-License-Identifier: MIT
214 * - with passed few options from dc->config
215 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
217 * - with passed latency values (passed in ns units) in dc-> bb override for
219 * - with passed latencies from VBIOS (in 100_ns units) if available for
221 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
223 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu()
234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()
240 dc->res_pool->res_cap->num_timing_generator; in dcn35_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c1 /* SPDX-License-Identifier: MIT */
248 * - with passed few options from dc->config
249 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
251 * - with passed latency values (passed in ns units) in dc-> bb override for
253 * - with passed latencies from VBIOS (in 100_ns units) if available for
255 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
257 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu()
268 dc->scratch.update_bw_bounding_box.clock_limits; in dcn351_update_bw_bounding_box_fpu()
274 dc->res_pool->res_cap->num_timing_generator; in dcn351_update_bw_bounding_box_fpu()
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/linux/drivers/i2c/busses/
H A Di2c-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
125 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
128 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
129 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
130 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
262 /* supported clk settings. values in Hz. */
602 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
613 bus->stop_ind = I2C_NO_STATUS_IND; in npcm_i2c_init_params()
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