Home
last modified time | relevance | path

Searched +full:clk +full:- +full:csr (Results 1 – 25 of 66) sorted by relevance

123

/linux/drivers/watchdog/
H A Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
31 #include <linux/clk.h>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
43 * something quite higher than 100 (or we need a proper high-res timer
46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
[all …]
/linux/drivers/clk/
H A Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
14 #include <linux/clk-provider.h>
32 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
34 return readl_relaxed(csr); in xgene_clk_read()
37 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
39 writel_relaxed(data, csr); in xgene_clk_write()
64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
84 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs-plat.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
15 #include <linux/pcs/pcs-xpcs.h>
22 #include "pcs-xpcs.h"
33 struct clk *cclk;
41 static u16 xpcs_mmio_addr_page(ptrdiff_t csr) in xpcs_mmio_addr_page() argument
43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
46 static ptrdiff_t xpcs_mmio_addr_offset(ptrdiff_t csr) in xpcs_mmio_addr_offset() argument
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
54 ptrdiff_t csr, ofs; in xpcs_mmio_read_reg_indirect() local
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx95-blk-ctl.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2024-2025 NXP
6 #include <dt-bindings/clock/nxp,imx94-clock.h>
7 #include <dt-bindings/clock/nxp,imx95-clock.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
34 struct clk *clk_apb;
352 struct device *dev = &pdev->dev; in imx95_bc_probe()
361 return -ENOMEM; in imx95_bc_probe()
362 bc->dev = dev; in imx95_bc_probe()
[all …]
/linux/drivers/dma/
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
7 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
[all …]
/linux/drivers/pci/controller/
H A Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
9 #include <linux/clk.h>
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
63 struct clk *clk; member
73 return readl(port->csr_base + reg); in xgene_pcie_readl()
78 writel(val, port->csr_base + reg); in xgene_pcie_writel()
91 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
93 cfg = bus->sysdata; in pcie_bus_to_port()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
24 by Control and Status Registers(CSR) module in the SoC. The CSR
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
[all …]
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
[all …]
/linux/drivers/mmc/host/
H A Dwbsd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/wbsd.c - Winbond W83L51xD SD/MMC driver
5 * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.
12 * - FIFO size field in FSR is always zero.
14 * - FIFO interrupts tend not to work as they should. Interrupts are
17 * - On APIC systems the FIFO empty interrupt is sometimes lost.
26 #include <linux/dma-mapping.h>
86 BUG_ON(host->config == 0); in wbsd_unlock_config()
88 outb(host->unlock_code, host->config); in wbsd_unlock_config()
89 outb(host->unlock_code, host->config); in wbsd_unlock_config()
[all …]
H A Dushc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - Only version 2 devices are supported.
9 * - Version 2 devices only support SDIO cards/devices (R2 response is
13 * [USHC] USB SD Host Controller specification (CS-118793-SP)
19 #include <linux/dma-mapping.h>
121 return usb_control_msg(ushc->usb_dev, usb_sndctrlpipe(ushc->usb_dev, 0), in ushc_hw_reset()
131 ret = usb_control_msg(ushc->usb_dev, usb_rcvctrlpipe(ushc->usb_dev, 0), in ushc_hw_get_caps()
133 0, 0, &ushc->caps, sizeof(ushc->caps), 100); in ushc_hw_get_caps()
137 ushc->caps = le32_to_cpu(ushc->caps); in ushc_hw_get_caps()
139 version = ushc->caps & USHC_GET_CAPS_VERSION_MASK; in ushc_hw_get_caps()
[all …]
/linux/drivers/tty/serial/
H A Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk.h>
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
225 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_read()
228 ret = readb(port->membase + (reg << port->regshift)); in sccnxp_read()
230 ndelay(s->chip->trwd); in sccnxp_read()
237 struct sccnxp_port *s = dev_get_drvdata(port->dev); in sccnxp_write()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-ipq806x.c23 #include <linux/clk.h>
85 (0x13c + (4 * (x - 2))))
111 struct clk *core_clk;
117 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
135 return -EINVAL; in get_clk_div_sgmii()
143 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
161 return -EINVAL; in get_clk_div_rgmii()
172 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
178 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
179 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-octeon-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <linux/clk.h>
8 #include <linux/i2c-smbus.h>
42 #define TWSI_CTL_STA 0x20 /* Controller-mode start, HW clears when done */
43 #define TWSI_CTL_STP 0x10 /* Controller-mode stop, HW clears when done */
104 #define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi)
105 #define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int)
106 #define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext)
107 #define OCTEON_REG_MODE(x) ((x)->roff.mode)
108 #define OCTEON_REG_BLOCK_CTL(x) ((x)->roff.block_ctl)
[all …]
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
58 #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
81 /* calculate the value of CS bits in CSR register on standard mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
89 /* calculate the value of CS bits in CSR register on fast mode */
95 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
[all …]
/linux/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
65 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
124 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ in tegra30_boot_secondary()
[all …]
/linux/drivers/regulator/
H A Dstm32-vrefbuf.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
22 /* STM32 VREFBUF CSR bitfields */
32 struct clk *clk; member
47 ret = pm_runtime_resume_and_get(priv->dev); in stm32_vrefbuf_enable()
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
64 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable()
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
[all …]
/linux/drivers/clk/qcom/
H A Dlpasscc-sm6115.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,sm6115-lpasscc.h>
27 .name = "lpass-audio-csr",
45 .name = "lpass-tcsr",
57 .compatible = "qcom,sm6115-lpassaudiocc",
60 .compatible = "qcom,sm6115-lpasscc",
69 const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); in lpasscc_sm6115_probe()
77 .name = "lpasscc-sm6115",
H A Dlpasscc-sc8280xp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
30 .name = "lpass-audio-csr",
48 .name = "lpass-tcsr",
60 .compatible = "qcom,sc8280xp-lpassaudiocc",
63 .compatible = "qcom,sc8280xp-lpasscc",
72 const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); in lpasscc_sc8280xp_probe()
80 .name = "lpasscc-sc8280xp",
/linux/arch/arm64/boot/dts/airoha/
H A Den7581.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/en7523-clk.h>
6 #include <dt-bindings/reset/airoha,en7581-reset.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
13 reserved-memory {
14 #address-cells = <2>;
[all …]
/linux/drivers/rtc/
H A Drtc-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene SoC Real Time Clock Driver
10 #include <linux/clk.h>
20 /* RTC CSR Registers */
38 struct clk *clk; member
47 rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); in xgene_rtc_read_time()
59 writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR); in xgene_rtc_set_time()
60 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ in xgene_rtc_set_time()
70 rtc_time64_to_tm(0, &alrm->time); in xgene_rtc_read_alarm()
71 alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; in xgene_rtc_read_alarm()
[all …]
/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * at91_udc -- driver for at91-series USB peripheral controller
25 #include <linux/clk.h>
33 #include <linux/mfd/syscon/atmel-matrix.h>
39 * This controller is simple and PIO-only. It's used in many AT91-series
41 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
76 EP_INFO("ep3-int",
91 __raw_readl((udc)->udp_baseaddr + (reg))
93 __raw_writel((val), (udc)->udp_baseaddr + (reg))
95 /*-------------------------------------------------------------------------*/
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
30 #include <linux/clk.h>
57 printk(KERN_ERR KBUILD_MODNAME ": %s: Error - " fmt, \
60 wiphy_err_ratelimited((dev)->hw->wiphy, "%s: Error - " fmt, \
63 wiphy_warn_ratelimited((dev)->hw->wiphy, "%s: Warning - " fmt, \
66 wiphy_info((dev)->hw->wiphy, "%s: Info - " fmt, \
71 wiphy_dbg((dev)->hw->wiphy, "%s: Debug - " fmt, \
74 wiphy_dbg((dev)->hw->wiphy, "%s: EEPROM recovery - " fmt, \
[all …]
/linux/drivers/cpuidle/
H A Dcpuidle-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
26 #include <linux/clk/tegra.h>
53 unsigned long cpu, lcpu, csr; in tegra_cpuidle_report_cpus_state() local
57 csr = flowctrl_read_cpu_csr(cpu); in tegra_cpuidle_report_cpus_state()
60 cpu, cpu_online(lcpu), csr); in tegra_cpuidle_report_cpus_state()
68 while (retries--) { in tegra_cpuidle_wait_for_secondary_cpus_parking()
74 * shutdown in order to power-off CPU's cluster safely. in tegra_cpuidle_wait_for_secondary_cpus_parking()
76 * it takes about 40-150us in average and over 1000us in in tegra_cpuidle_wait_for_secondary_cpus_parking()
[all …]

123