Lines Matching +full:clk +full:- +full:csr
1 /* SPDX-License-Identifier: GPL-2.0 */
4 #include <linux/clk.h>
8 #include <linux/i2c-smbus.h>
42 #define TWSI_CTL_STA 0x20 /* Controller-mode start, HW clears when done */
43 #define TWSI_CTL_STP 0x10 /* Controller-mode stop, HW clears when done */
104 #define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi)
105 #define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int)
106 #define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext)
107 #define OCTEON_REG_MODE(x) ((x)->roff.mode)
108 #define OCTEON_REG_BLOCK_CTL(x) ((x)->roff.block_ctl)
109 #define OCTEON_REG_BLOCK_STS(x) ((x)->roff.block_sts)
110 #define OCTEON_REG_BLOCK_FIFO(x) ((x)->roff.block_fifo)
128 struct clk *clk; member
156 * octeon_i2c_reg_write - write an I2C core register
161 * The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
168 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_write()
170 tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_write()
171 if (--tries < 0) in octeon_i2c_reg_write()
182 * octeon_i2c_reg_read - read lower bits of an I2C core register
188 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
196 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_read()
198 tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); in octeon_i2c_reg_read()
199 if (--tries < 0) { in octeon_i2c_reg_read()
202 *error = -EIO; in octeon_i2c_reg_read()
218 * octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
225 return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c)); in octeon_i2c_read_int()
229 * octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
235 octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c)); in octeon_i2c_write_int()
242 * octeon_i2c_is_otx2 - check for chip ID
249 u32 chip_id = FIELD_GET(PCI_SUBSYS_MASK, pdev->subsystem_device); in octeon_i2c_is_otx2()