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/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
33 bool "Flash chip driver advanced configuration options"
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
[all …]
/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
67 * Chip-select row
70 accessed. Common chip-select rows for single channel are 64 bits, for
[all …]
/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_hipd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * of PCI-SCSI IO processors.
6 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx>
10 * Copyright (C) 1998-2000 Gerard Roudier
13 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 * Stefan Esser <se@mi.Uni-Koeln.de>
25 *-----------------------------------------------------------------------------
55 while (n-- > 0) in sym_printl_hex()
62 sym_print_addr(cp->cmd, "%s: ", label); in sym_print_msg()
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/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
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H A Dncr53c8xx.rst1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
28 8.2 Set wide size
53 10.2.13 Max wide
64 10.4 PCI configuration fix-up boot option
74 14.3 Using only 8 bit devices with a WIDE SCSI controller.
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
89 18.2 NCR chip in Big Endian mode of operations
97 - Gerard Roudier <groudier@free.fr>
[all …]
H A Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
14 Descriptor Block) requests that can be stored in the RISC chip
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
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H A D53c700.rst1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
45 the SCSI Id from the card bios or whether the chip is wired for
54 asynchronous dividers for the chip. As a general rule of thumb,
56 consistent with the best operation of the chip (although some choose
58 of an extra clock chip). The best operation clock speeds are:
[all …]
/linux/drivers/scsi/
H A Desp_scsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */
40 /* ESP config reg 1, read-write, found on all ESP chips */
42 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
48 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
52 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */
55 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
58 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */
63 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
65 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
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H A Dncr53c8xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** Device driver for the PCI-SCSI NCR538XX controller family.
8 **-----------------------------------------------------------------------------
22 ** Stefan Esser <se@mi.Uni-Koeln.de>
27 **-----------------------------------------------------------------------------
38 ** Support for Fast-20 scsi.
42 ** Support for Fast-40 scsi.
43 ** Support for on-Board RAM.
46 ** Full support for scsi scripts instructions pre-fetching.
57 ** Low PCI traffic for command handling when on-chip RAM is present.
[all …]
/linux/Documentation/fb/
H A Darkfb.rst2 arkfb - fbdev driver for ARK Logic chips
9 ARK 2000PV chip
12 - only BIOS initialized VGA devices supported
13 - probably not working on big endian
32 wide fonts only (hardware limitation) and 16bit tall fonts (driver
39 8bit wide fonts only (driver limitation).
59 * acceleration support (8514-like 2D)
67 --
/linux/include/linux/mtd/
H A Ddoc2000.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux driver for Disk-On-Chip devices
6 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
7 * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
8 * Copyright © 2002-2003 SnapGear Inc
76 * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
77 * On PPC, it's mmap'd and 16-bit wide.
161 char floor, chip; member
187 unsigned long mfr; /* Flash IDs - only one type of flash per device */
192 char interleave; /* Internal interleaving - Millennium Plus style */
/linux/Documentation/devicetree/bindings/mfd/
H A Dwm831x.txt3 System PMICs with a wide range of additional features.
7 - compatible : One of the following chip-specific strings:
16 - reg : I2C slave address when connected using I2C, chip select number
19 - gpio-controller : Indicates this device is a GPIO controller.
20 - #gpio-cells : Must be 2. The first cell is the pin number and the
23 - interrupts : The interrupt line the IRQ signal for the device is
26 - interrupt-controller : wm831x devices contain interrupt controllers and
28 - #interrupt-cells: Must be 2. The first cell is the IRQ number, and the
30 ../interrupt-controller/interrupts.txt
32 Optional sub-nodes:
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - J. Neuschäfer <j.ne@posteo.net>
14 controlling chip-wide low-power states as well as peripheral clock gating.
20 For "fsl,mpc8349-pmc", sleep specifiers consist of one cell. For each bit that
25 For "fsl,mpc8536-pmc", sleep specifiers consist of three cells, the third of
27 resume. The first two cells are as described for fsl,mpc8548-pmc. This
31 For "fsl,mpc8548-pmc" or "fsl,mpc8641d-pmc", Sleep specifiers consist of one
33 into DEVDISR2, if present -- this cell should be zero or absent if the
[all …]
/linux/drivers/scsi/arm/
H A Dfas216.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2000 Russell King
114 #define CNTL1_CID (7 << 0) /* Chip ID */
123 #define CLKF_F37MHZ 0x00 /* 35.01 - 40 MHz */
125 #define CLKF_F12MHZ 0x03 /* 10.01 - 15 MHz */
126 #define CLKF_F17MHZ 0x04 /* 15.01 - 20 MHz */
127 #define CLKF_F22MHZ 0x05 /* 20.01 - 25 MHz */
128 #define CLKF_F27MHZ 0x06 /* 25.01 - 30 MHz */
129 #define CLKF_F32MHZ 0x07 /* 30.01 - 35 MHz */
131 /* Chip test register (write) */
[all …]
/linux/sound/isa/sb/
H A Dsb_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data) in snd_sbmixer_write() argument
19 outb(reg, SBP(chip, MIXER_ADDR)); in snd_sbmixer_write()
21 outb(data, SBP(chip, MIXER_DATA)); in snd_sbmixer_write()
24 dev_dbg(chip->car in snd_sbmixer_write()
28 snd_sbmixer_read(struct snd_sb * chip,unsigned char reg) snd_sbmixer_read() argument
440 snd_sbmixer_add_ctl(struct snd_sb * chip,const char * name,int index,int type,unsigned long value) snd_sbmixer_add_ctl() argument
693 snd_sbmixer_init(struct snd_sb * chip,const struct sbmix_elem * controls,int controls_count,const unsigned char map[][2],int map_count,char * name) snd_sbmixer_init() argument
726 snd_sbmixer_new(struct snd_sb * chip) snd_sbmixer_new() argument
881 save_mixer(struct snd_sb * chip,const unsigned char * regs,int num_regs) save_mixer() argument
890 restore_mixer(struct snd_sb * chip,const unsigned char * regs,int num_regs) restore_mixer() argument
899 snd_sbmixer_suspend(struct snd_sb * chip) snd_sbmixer_suspend() argument
926 snd_sbmixer_resume(struct snd_sb * chip) snd_sbmixer_resume() argument
[all...]
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
[all …]
/linux/drivers/pwm/
H A Dpwm-microchip-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
28 * - The PWM period is set for the whole IP block not per channel. The driver
63 static inline struct mchp_core_pwm_chip *to_mchp_core_pwm(struct pwm_chip *chip) in to_mchp_core_pwm() argument
65 return pwmchip_get_drvdata(chip); in to_mchp_core_pwm()
68 static void mchp_core_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, in mchp_core_pwm_enable() argument
71 struct mchp_core_pwm_chip *mchp_core_pwm = to_mchp_core_pwm(chip); in mchp_core_pwm_enable()
[all …]
/linux/include/video/
H A Dpmag-ba-fb.h2 * linux/include/video/pmag-ba-fb.h
4 * TURBOchannel PMAG-BA Color Frame Buffer (CFB) card support,
6 * Michael Engel <engel@unix-ag.org>,
20 #define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */
23 /* Bt459 register offsets, byte-wide registers. */
/linux/drivers/gpio/
H A Dgpio-syscon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 /* SYSCON driver is designed to use 32-bit wide registers */
25 * struct syscon_gpio_data - Configuration for the device.
43 int (*set)(struct gpio_chip *chip, unsigned int offset,
48 struct gpio_chip chip; member
55 static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) in syscon_gpio_get() argument
57 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); in syscon_gpio_get()
61 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; in syscon_gpio_get()
63 ret = regmap_read(priv->syscon, in syscon_gpio_get()
71 static int syscon_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) in syscon_gpio_set() argument
[all …]
/linux/sound/pci/echoaudio/
H A Dechoaudio.h3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
34 +-----------+
35 record | |<-------------------- Inputs
36 <-------| | |
39 ------->| | +-------+
40 play | |--->|monitor|-------> Outputs
41 +-----------+ | mixer |
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_nsp_eth.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
128 dst[ETH_ALEN - i - 1] = src[i]; in nfp_eth_copy_mac_reverse()
139 port = le64_to_cpu(src->port); in nfp_eth_port_translate()
140 state = le64_to_cpu(src->state); in nfp_eth_port_translate()
142 dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); in nfp_eth_port_translate()
143 dst->index = index; in nfp_eth_port_translate()
144 dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
145 dst->base = index % NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
146 dst->lanes = FIELD_GET(NSP_ETH_PORT_LANES, port); in nfp_eth_port_translate()
[all …]
/linux/Documentation/admin-guide/
H A Drtc.rst8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
20 so it's not very portable to non-x86 systems.
23 supported by a wide variety of RTC chips on all systems.
35 Old PC/AT-Compatible driver: /dev/rtc
36 --------------------------------------
44 a few ways (enabling longer alarm periods, and wake-from-hibernate).
59 the type of interrupt (update-done, alarm-rang, or periodic) that was
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,zynqmp-ocmc-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
15 and recover from a single-bit memory fault.On a write, if all bytes are
17 the write-data that is written into the data RAM. If one or more bytes are
[all …]
/linux/arch/mips/alchemy/devboards/
H A Dbcsr.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
8 * All registers are 16bits wide with 32bit spacing.
19 #include <asm/mach-db1x00/bcsr.h>
27 static int bcsr_csc_base; /* linux-irq of first cascaded irq */
41 (0x04 * (i - BCSR_HEXLEDS)); in bcsr_init()
94 struct irq_chip *chip = irq_desc_get_chip(d); in bcsr_csc_handler() local
96 chained_irq_enter(chip, d); in bcsr_csc_handler()
98 chained_irq_exit(chip, d); in bcsr_csc_handler()
103 unsigned short v = 1 << (d->irq - bcsr_csc_base); in bcsr_irq_mask()
[all …]
/linux/Documentation/hwmon/
H A Dvexpress.rst15 - http://infocenter.arm.com/help/topic/com.arm.doc.subset.boards.express/index.html
17 * Section "4.4.14. System Configuration registers" of the V2M-P1 TRM:
19 - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0447-/index.html
24 -----------
28 from a wide range of boards, each of them containing (apart of the main
29 chip/FPGA) a number of microcontrollers responsible for platform
39 As these devices are non-discoverable, they must be described in a Device

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