Lines Matching +full:chip +full:- +full:wide

1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
18  * 4. Neither the name of the author nor the names of any co-contributors
37  * Definitions for the built-in copper PHY can be found in vgphy.h.
41  * using 32-bit I/O cycles, but some of them are less than 32 bits
42  * wide. Go figure.
119 #define VGE_SSTIMER		0x74	/* single-shot timer */
121 #define VGE_CHIPCFG0		0x78	/* chip config A */
122 #define VGE_CHIPCFG1		0x79	/* chip config B */
123 #define VGE_CHIPCFG2		0x7A	/* chip config C */
124 #define VGE_CHIPCFG3		0x7B	/* chip config D */
140 #define VGE_CHIPSTRAP		0x99	/* Chip jumper strapping status */
142 #define VGE_DIAGSTS		0x9C	/* Chip diagnostic status */
143 #define VGE_DBGCTL		0x9E	/* Chip debug control */
144 #define VGE_DIAGCTL		0x9F	/* Chip diagnostic control */
233 #define VGE_CR3_INT_SWPEND		0x01 /* disable multi-level int bits */
386  * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389  * - The behavior of the interrupt holdoff timer register at offset
393  * - The behavior the WOL pattern programming registers at offset
454 /* Chip config register A */
456 #define VGE_CHIPCFG0_PACPI	0x01	/* pre-ACPI wakeup function */
462 /* Chip config register B */
474 /* Chip config register C */
478 /* Chip config register D */
537 #define VGE_TXCFG_NONBLK	0x02	/* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR	0x0C	/* non-blocking threshold */
590 #define	VGE_MIB_CNT		(VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
635 #define VGE_EECSR_ECS		0x08	/* chip select pin */
648 /* Chip operation and diagnostic control register */
679  * Normally, the chip requires the driver to issue a TX poll command