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/linux/drivers/usb/renesas_usbhs/
H A Dfifo.c1 // SPDX-License-Identifier: GPL-1.0+
15 #define usbhsf_get_cfifo(p) (&((p)->fifo_info.cfifo))
17 #define usbhsf_fifo_is_busy(f) ((f)->pipe) /* see usbhs_pipe_select_fifo */
24 INIT_LIST_HEAD(&pkt->node); in usbhs_pkt_init()
32 struct usbhs_priv *priv = usbhs_pipe_to_priv(pkt->pipe); in usbhsf_null_handle()
37 return -EINVAL; in usbhsf_null_handle()
48 void *buf, int len, int zero, int sequence) in usbhs_pkt_push() argument
62 if (!pipe->handler) { in usbhs_pkt_push()
64 pipe->handler = &usbhsf_null_handler; in usbhs_pkt_push()
67 list_move_tail(&pkt->node, &pipe->list); in usbhs_pkt_push()
[all …]
/linux/drivers/isdn/hardware/mISDN/
H A Dhfcsusb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * mISDN driver for Colognechip HFC-S USB chip
5 * Copyright 2001 by Peter Sprenger (sprenger@moving-bytes.de)
6 * Copyright 2008 by Martin Bachem (info@bachem-it.com)
10 * H - l1 driver flags described in hfcsusb.h
11 * G - common mISDN debug flags described at mISDNhw.h
16 * Revision: 0.3.3 (socket), 2008-11-05
34 MODULE_DESCRIPTION("mISDN driver for Colognechip HFC-S USB chip");
46 static void hfcsusb_start_endpoint(struct hfcsusb *hw, int channel);
47 static void hfcsusb_stop_endpoint(struct hfcsusb *hw, int channel);
[all …]
H A Dhfcpci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * hfcpci.c low level driver for CCD's hfc-pci based cards
8 * type approval valid for HFC-S PCI A based card
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
21 * Give the number of samples for each fifo process.
52 MODULE_DESCRIPTION("mISDN driver for CCD's hfc-pci based cards");
102 void *fifos; /* FIFO memory */
104 /* marker saving last b-fifo frame count */
143 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE; in enable_hwirq()
144 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2); in enable_hwirq()
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H A Dhfcmulti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
7 * Peter Sprenger (sprengermoving-bytes.de)
9 * inspired by existing hfc-pci driver:
10 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
22 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
23 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
24 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
26 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
38 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
[all …]
/linux/drivers/mailbox/
H A Dcix-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
23 /* [0~7] Fast channel
24 * [8] doorbell base channel
25 * [9]fifo base channel
26 * [10] register base channel
105 * For the REG and FIFO types of transfers, the message format is as follows:
119 if (priv->use_shmem) in cix_mbox_write()
120 iowrite32(val, priv->base + offset - CIX_SHMEM_OFFSET); in cix_mbox_write()
122 iowrite32(val, priv->base + offset); in cix_mbox_write()
127 if (priv->use_shmem) in cix_mbox_read()
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in csio_t5_pcie_intr_handler()
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/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
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H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
65 /* maximum depth of RX/TX FIFO */
69 * struct ep93xx_spi - EP93xx SPI controller structure
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
77 * @dma_rx: RX DMA channel
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/linux/drivers/crypto/
H A Dtalitos.h1 /* SPDX-License-Identifier: BSD-3-Clause */
5 * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
20 __be16 len; /* length */ member
39 struct talitos_ptr ptr[7]; /* ptr/len pair array */
43 #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
46 * talitos_edesc - s/w-extended descriptor
74 * talitos_request - descriptor submission request
88 /* per-channel fifo management */
92 /* request fifo */
93 struct talitos_request *fifo; member
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/linux/drivers/dma/dw/
H A Didma32.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2013,2018,2020-2021 Intel Corporation
38 struct device *slave = dwc->chan.slave; in idma32_get_slave_devfn()
43 return to_pci_dev(slave)->devfn; in idma32_get_slave_devfn()
48 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in idma32_initialize_chan_xbar()
54 /* DMA Channel ID Configuration register must be programmed first */ in idma32_initialize_chan_xbar()
58 value |= dwc->chan.chan_id; in idma32_initialize_chan_xbar()
62 /* Configure channel attributes */ in idma32_initialize_chan_xbar()
63 value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id)); in idma32_initialize_chan_xbar()
69 switch (dwc->direction) { in idma32_initialize_chan_xbar()
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/linux/drivers/misc/
H A Dhpilo.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
52 static inline int mk_entry(int id, int len) in mk_entry() argument
54 int qlen = len & 7 ? (len >> 3) + 1 : len >> 3; in mk_entry()
64 * FIFO queues, shared with hardware.
75 struct fifo *fifo_q = FIFOBARTOHANDLE(fifobar); in fifo_enqueue()
79 spin_lock_irqsave(&hw->fifo_lock, flags); in fifo_enqueue()
80 if (!(fifo_q->fifobar[(fifo_q->tail + 1) & fifo_q->imask] in fifo_enqueue()
82 fifo_q->fifobar[fifo_q->tail & fifo_q->imask] |= in fifo_enqueue()
83 (entry & ENTRY_MASK_NOSTATE) | fifo_q->merge; in fifo_enqueue()
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/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
59 /* CxLBAR DMA channel x linked_list base address register */
62 /* CxCIDCFGR DMA channel x CID register */
76 /* CxSEMCR DMA channel x semaphore control register */
80 /* CxFCR DMA channel x flag clear register */
88 /* CxSR DMA channel x status register */
99 /* CxCR DMA channel x control register */
[all …]
H A Dstm32-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
16 #include <linux/dma-mapping.h>
31 #include "../virt-dma.h"
43 #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
49 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
97 /* DMA stream x FIFO control register */
100 #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
116 /* DMA FIFO threshold selection */
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dfw.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
71 val = rtw_read32_mask(rtwdev, reg->addr, reg->mask); in _rtw_fw_dump_dbg_info()
74 reg->desc, reg->addr, reg->mask, val); in _rtw_fw_dump_dbg_info()
100 sub_cmd_id = c2h->payload[0]; in rtw_fw_c2h_cmd_handle_ext()
148 struct rtw_c2h_ra_rpt *ra_rpt = (struct rtw_c2h_ra_rpt *)ra_data->payload; in rtw_fw_ra_report_iter()
149 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_fw_ra_report_iter()
154 mac_id = ra_rpt->mac_id; in rtw_fw_ra_report_iter()
155 if (si->mac_id != mac_id) in rtw_fw_ra_report_iter()
158 si->ra_report.txrate.flags = 0; in rtw_fw_ra_report_iter()
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/linux/sound/firewire/
H A Damdtp-am824.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AM824 format in Audio and Music Data Transmission Protocol (IEC 61883-6)
6 * Copyright (c) 2015 Takashi Sakamoto <o-takashi@sakamocchi.jp>
11 #include "amdtp-am824.h"
15 /* "Clock-based rate control mode" is just supported. */
42 * amdtp_am824_set_parameters - set stream parameters
46 * as AM824 multi-bit linear audio
47 * @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
58 struct amdtp_am824 *p = s->protocol; in amdtp_am824_set_parameters()
64 return -EINVAL; in amdtp_am824_set_parameters()
[all …]
/linux/drivers/rpmsg/
H A Dqcom_glink_smem.c1 // SPDX-License-Identifier: GPL-2.0
56 void *fifo; member
66 struct qcom_glink_smem *smem = pipe->smem; in glink_smem_rx_avail()
67 size_t len; in glink_smem_rx_avail() local
68 void *fifo; in glink_smem_rx_avail() local
72 if (!pipe->fifo) { in glink_smem_rx_avail()
73 fifo = qcom_smem_get(smem->remote_pid, in glink_smem_rx_avail()
74 SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len); in glink_smem_rx_avail()
75 if (IS_ERR(fifo)) { in glink_smem_rx_avail()
76 pr_err("failed to acquire RX fifo handle: %ld\n", in glink_smem_rx_avail()
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H A Dqcom_glink_rpm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
27 #define RPM_TOC_MAX_ENTRIES ((RPM_TOC_SIZE - sizeof(struct rpm_toc)) / \
54 void __iomem *fifo; member
75 head = readl(pipe->head); in glink_rpm_rx_avail()
76 tail = readl(pipe->tail); in glink_rpm_rx_avail()
79 return pipe->native.length - tail + head; in glink_rpm_rx_avail()
81 return head - tail; in glink_rpm_rx_avail()
89 size_t len; in glink_rpm_rx_peek() local
91 tail = readl(pipe->tail); in glink_rpm_rx_peek()
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/linux/arch/mips/alchemy/common/
H A Ddma.c4 * A DMA channel allocator for Au1x00. API is modeled loosely off of
9 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
40 #include <asm/mach-au1x00/au1000.h>
41 #include <asm/mach-au1x00/au1000_dma.h>
55 * done interrupt, you won't know the irq number until the DMA channel is
59 /* DMA Channel register block spacing */
65 {.dev_id = -1,},
66 {.dev_id = -1,},
67 {.dev_id = -1,},
68 {.dev_id = -1,},
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/linux/drivers/tty/
H A Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
71 /* Default channel for the early console */
80 * and space becoming available in TX FIFO.
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
121 * @fdc_name: FDC name (not for base of channel names).
123 * @ports: Per-channel data.
125 * FIFO.
129 * @tx_fifo: TX FIFO size.
[all …]
/linux/drivers/rapidio/devices/
H A Dtsi721.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
47 * tsi721_lcread - read from local SREP config space
51 * @len: Length (in bytes) of the maintenance transaction
56 * Returns: %0 on success or %-EINVAL on failure.
59 int len, u32 *data) in tsi721_lcread() argument
61 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
63 if (len != sizeof(u32)) in tsi721_lcread()
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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-drv.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
20 #include "xgbe-common.h"
67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) { in xgbe_free_channels()
68 if (!pdata->channel[i]) in xgbe_free_channels()
71 kfree(pdata->channel[i]->rx_ring); in xgbe_free_channels()
72 kfree(pdata->channel[i]->tx_ring); in xgbe_free_channels()
73 kfree(pdata->channel[i]); in xgbe_free_channels()
75 pdata->channel[i] = NULL; in xgbe_free_channels()
78 pdata->channel_count = 0; in xgbe_free_channels()
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/linux/drivers/comedi/drivers/
H A Dpcl818.c1 // SPDX-License-Identifier: GPL-2.0
6 * Description: Advantech PCL-818 cards, PCL-718
8 * Devices: [Advantech] PCL-818L (pcl818l), PCL-818H (pcl818h),
9 * PCL-818HD (pcl818hd), PCL-818HG (pcl818hg), PCL-818 (pcl818),
10 * PCL-718 (pcl718)
14 * Differences are only at maximal sample speed, range list and FIFO
17 * only mode 0. If DMA/FIFO/INT are disabled then AI support only mode 0.
18 * PCL-818HD and PCL-818HG support 1kword FIFO. Driver support this FIFO
37 * Options for PCL-818L:
38 * [0] - IO Base
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/linux/drivers/dma/
H A Dtxx9dmac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * This DMAC have four channels and one FIFO buffer. Each channel can
17 * be configured for memory-memory or device-memory transfer, but only
18 * one channel can do alignment-free memory-memory transfer at a time
19 * while the channel should occupy the FIFO buffer for effective
22 * Instead of dynamically assign the FIFO buffer to channels, I chose
23 * make one dedicated channel for memory-memory transfer. The
24 * dedicated channel is public. Other channels are private and used
26 * DMA channel.
56 * Redefine this macro to handle differences between 32- and 64-bit
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/linux/drivers/char/xillybus/
H A Dxillyusb.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * a pipe between a hardware FIFO in the programmable logic and a device
76 int fill; /* Number of bytes in the FIFO */
107 struct xillyfifo fifo; member
161 unsigned int len; member
219 * calls to each on the same FIFO is not allowed) however it's OK to have
220 * threads calling each of the two functions once on the same FIFO, and
224 static int fifo_write(struct xillyfifo *fifo, in fifo_write() argument
225 const void *data, unsigned int len, in fifo_write() argument
229 unsigned int todo = len; in fifo_write()
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/linux/drivers/ata/
H A Dsata_qstor.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_qstor.c - Pacific Digital Corporation QStor SATA
11 * as Documentation/driver-api/libata.rst
42 QS_HST_SFF = 0x0100, /* host status fifo offset */
46 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
50 /* per-channel register offsets */
53 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
54 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
55 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
56 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
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