Lines Matching +full:channel +full:- +full:fifo +full:- +full:len

1 /* SPDX-License-Identifier: GPL-2.0-only */
16  * This DMAC have four channels and one FIFO buffer.  Each channel can
17  * be configured for memory-memory or device-memory transfer, but only
18  * one channel can do alignment-free memory-memory transfer at a time
19  * while the channel should occupy the FIFO buffer for effective
22  * Instead of dynamically assign the FIFO buffer to channels, I chose
23  * make one dedicated channel for memory-memory transfer.  The
24  * dedicated channel is public.  Other channels are private and used
26  * DMA channel.
56  * Redefine this macro to handle differences between 32- and 64-bit
77 	TXX9_DMA_REG32(CCR);	/* Channel Control Register */
78 	TXX9_DMA_REG32(CSR);	/* Channel Status Register */
92 	/* per-channel registers */
190 	return ddev->have_64bit_regs;  in __is_dmac64()
195 	return __is_dmac64(dc->ddev);  in is_dmac64()
199 /* Hardware descriptor definition. (for simple-chain) */
232 	size_t				len;  member
239 	return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;  in txx9dmac_chan_INTENT()
244 	dc->ccr |= TXX9_DMA_CCR_INTENT;  in txx9dmac_chan_set_INTENT()
254 	dc->ccr |= TXX9_DMA_CCR_SMPCHN;  in txx9dmac_chan_set_SMPCHN()
278 		desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT;  in txx9dmac_desc_set_INTENT()
280 		desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT;  in txx9dmac_desc_set_INTENT()
292 		desc->hwdesc.SAIR = sai;  in txx9dmac_desc_set_nosimple()
293 		desc->hwdesc.DAIR = dai;  in txx9dmac_desc_set_nosimple()
294 		desc->hwdesc.CCR = ccr;  in txx9dmac_desc_set_nosimple()
296 		desc->hwdesc32.SAIR = sai;  in txx9dmac_desc_set_nosimple()
297 		desc->hwdesc32.DAIR = dai;  in txx9dmac_desc_set_nosimple()
298 		desc->hwdesc32.CCR = ccr;  in txx9dmac_desc_set_nosimple()