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/linux/drivers/char/xillybus/
H A Dxillybus_core.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/dma-mapping.h>
52 #define XILLYMSG_OPCODE_RELEASEBUF 1
75 * register_mutex is endpoint-specific, and is held when non-atomic
87 * wr_mutex -> rd_mutex -> register_mutex -> wr_spinlock -> rd_spinlock
96 msg_dir = buf[0] & 1; in malformed_message()
97 msg_channel = (buf[0] >> 1) & 0x7ff; in malformed_message()
99 msg_data = buf[1] & 0xfffffff; in malformed_message()
101 dev_warn(endpoint->dev, in malformed_message()
102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
[all …]
/linux/drivers/media/platform/allegro-dvt/
H A Dallegro-core.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/xlnx-vcu.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/v4l2-mem2mem.h>
31 #include <media/videobuf2-dma-contig.h>
32 #include <media/videobuf2-v4l2.h>
34 #include "allegro-mail.h"
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 # define SSI_AUTOIDLE (1 << 0)
20 # define SSI_SOFTRESET (1 << 1)
22 # define SSI_SIDLEMODE_NO (1 << 3)
23 # define SSI_SIDLEMODE_SMART (1 << 4)
26 # define SSI_MIDLEMODE_NO (1 << 12)
27 # define SSI_MIDLEMODE_SMART (1 << 13)
30 # define SSI_RESETDONE 1
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
[all …]
/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
57 #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1)
58 #define TAS5086_CLOCK_VALID (1 << 0)
65 #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */
[all …]
/linux/drivers/ptp/
H A Dptp_clockmatrix.c1 // SPDX-License-Identifier: GPL-2.0+
27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
33 * over-rides any automatic selection
41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count); in idtcm_read()
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count); in idtcm_write()
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data; in contains_full_configuration()
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH); in contains_full_configuration()
73 full_count = (scratch - GPIO_USER_CONTROL) - in contains_full_configuration()
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4; in contains_full_configuration()
[all …]
H A Dptp_idt82p33.c1 // SPDX-License-Identifier: GPL-2.0
25 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
46 return regmap_bulk_read(idt82p33->regmap, regaddr, buf, count); in idt82p33_read()
52 return regmap_bulk_write(idt82p33->regmap, regaddr, buf, count); in idt82p33_write()
65 nsec |= buf[2 - i]; in idt82p33_byte_array_to_timespec()
71 sec |= buf[8 - i]; in idt82p33_byte_array_to_timespec()
74 ts->tv_sec = sec; in idt82p33_byte_array_to_timespec()
75 ts->tv_nsec = nsec; in idt82p33_byte_array_to_timespec()
85 nsec = ts->tv_nsec; in idt82p33_timespec_to_byte_array()
86 sec = ts->tv_sec; in idt82p33_timespec_to_byte_array()
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
/linux/drivers/iio/adc/
H A Dad7476.c1 // SPDX-License-Identifier: GPL-2.0
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
31 struct iio_chan_spec channel[2]; member
80 if (!st->convst_gpio) in ad7091_convst()
83 gpiod_set_value(st->convst_gpio, 0); in ad7091_convst()
84 udelay(1); /* CONVST pulse width: 10 ns min */ in ad7091_convst()
85 gpiod_set_value(st->convst_gpio, 1); in ad7091_convst()
86 udelay(1); /* Conversion time: 650 ns max */ in ad7091_convst()
92 struct iio_dev *indio_dev = pf->indio_dev; in ad7476_trigger_handler()
98 b_sent = spi_sync(st->spi, &st->msg); in ad7476_trigger_handler()
[all …]
/linux/drivers/firmware/arm_scmi/transports/
H A Doptee.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2021 Linaro Ltd.
22 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
30 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer
32 * [in] value[0].a: Channel handle
35 * already identified and bound to channel handle in both SCMI agent
36 * and SCMI server (OP-TEE) parts.
37 * The memory uses SMT header to carry SCMI meta-data (protocol ID and
40 PTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1,
43 * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message
[all …]
/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
64 return 1; in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
25 * 1 => MSI
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
64 return 1; in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
[all …]
H A Drx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
47 struct efx_nic *efx = rx_queue->efx; in efx_rx_packet__check_len()
48 unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding; in efx_rx_packet__check_len()
56 rx_buf->flags |= EFX_RX_PKT_DISCARD; in efx_rx_packet__check_len()
59 netif_err(efx, rx_err, efx->net_dev, in efx_rx_packet__check_len()
63 efx_rx_queue_channel(rx_queue)->n_rx_overlength++; in efx_rx_packet__check_len()
67 static struct sk_buff *efx_rx_mk_skb(struct efx_channel *channel, in efx_rx_mk_skb() argument
72 struct efx_nic *efx = channel->efx; in efx_rx_mk_skb()
[all …]
/linux/drivers/usb/musb/
H A Dmusbhsdma.c1 // SPDX-License-Identifier: GPL-2.0
3 * MUSB OTG driver - support for Mentor's DMA controller
6 * Copyright (C) 2005-2007 by Texas Instruments
35 /* control register (16-bit): */
37 #define MUSB_HSDMA_TRANSMIT_SHIFT 1
45 #define MUSB_HSDMA_BURSTMODE_INCR4 1
54 struct dma_channel channel; member
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; member
74 static void dma_channel_release(struct dma_channel *channel);
78 struct musb *musb = controller->private_data; in dma_controller_stop()
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ad5770r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandru Tachici <alexandru.tachici@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
24 maxItems: 1
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
50 * Implement support for Line-in capture on SB Live 24bit.
65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
26 maxItems: 1
29 maxItems: 1
31 "#address-cells":
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/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
42 * 1 = Capture output 1.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
46 * 1 = Capture output 1.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
50 * 1 = Capture output 1.
[all …]
/linux/drivers/hwmon/
H A Dltc2992.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * LTC2992 - Dual Wide Range Power Monitor
108 #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
141 .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
153 .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
165 .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
177 .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
194 ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len); in ltc2992_read_reg()
200 val |= regvals[reg_len - i - 1] << (i * 8); in ltc2992_read_reg()
211 regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF; in ltc2992_write_reg()
[all …]
H A Dcorsair-cpro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * corsair-cpro.c - Linux driver for Corsair Commander Pro
33 #define CTL_GET_FW_VER 0x02 /* returns the firmware version in bytes 1-3 */
34 #define CTL_GET_BL_VER 0x06 /* returns the bootloader version in bytes 1-2 */
36 * returns in bytes 1-4 for each temp sensor:
38 * 1 connected
41 * send: byte 1 is channel, rest zero
42 * rcv: returns temp for channel in centi-degree celsius
43 * in bytes 1 and 2
47 * send: byte 1 is rail number: 0 = 12v, 1 = 5v, 2 = 3.3v
[all …]
H A Dnct7904.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
42 #define FANIN_MAX 12 /* Counted from 1 */
45 #define FANCTL_MAX 4 /* Counted from 1 */
46 #define TCPU_MAX 8 /* Counted from 1 */
47 #define TEMP_MAX 4 /* Counted from 1 */
48 #define SMI_STS_MAX 10 /* Counted from 1 */
59 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
60 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
61 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
[all …]
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
[all …]
/linux/Documentation/ABI/testing/
H A Dconfigfs-most9 # mount -t configfs none /sys/kernel/config/
19 configure the buffer size for this channel
22 configure the sub-buffer size for this channel
28 channel
32 this channel
51 channel
52 name of the channel the link is to be attached to
58 write '1' to this attribute to trigger the
60 configuration, the creation is post-poned until
64 write '1' to this attribute to destroy an
[all …]
/linux/Documentation/driver-api/dmaengine/
H A Ddmatest.rst15 The dmatest module can be configured to test a specific channel. It can also
17 competing for the same channel.
21 capability of the following: DMA_MEMCPY (memory-to-memory), DMA_MEMSET
22 (const-to-memory or memory-to-memory, when emulated), DMA_XOR, DMA_PQ.
28 Part 1 - How to build the test module
33 Device Drivers -> DMA Engine support -> DMA Test client
38 Part 2 - When dmatest is built as a module
43 % modprobe dmatest timeout=2000 iterations=1 channel=dma0chan0 run=1
49 % echo 1 > /sys/module/dmatest/parameters/iterations
50 % echo dma0chan0 > /sys/module/dmatest/parameters/channel
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