Lines Matching +full:channel +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
26 4: I2C port 1
32 10: Multi-Channel Display Engine MCDE RX
34 12: UART port 1
42 20: SLIMbus or HSI channel 0
43 21: SLIMbus or HSI channel 1
44 22: SLIMbus or HSI channel 2
45 23: SLIMbus or HSI channel 3
52 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
53 31: MSP port 0 or SLIMbus channel 0
54 32: SD/MMC controller 1
57 35: SPI controller 1
60 38: USB OTG in/out endpoints 1 & 9
68 46: SLIMbus channel 8 or Multimedia DSP SXA6
69 47: SLIMbus channel 9 or Multimedia DSP SXA7
70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
72 50: Hash Accelerator 1 TX
74 52: SLIMbus or HSI channel 4
75 53: SLIMbus or HSI channel 5
76 54: SLIMbus or HSI channel 6
77 55: SLIMbus or HSI channel 7
88 a fixed channel is allocated, and indicated by setting bit 3 in the
93 0x00000001 (bit 0) - mode:
94 Logical channel when unset
95 Physical channel when set
96 0x00000002 (bit 1) - direction:
99 0x00000004 (bit 2) - endianness:
102 0x00000008 (bit 3) - use fixed channel:
103 Use automatic channel selection when unset
105 0x00000010 (bit 4) - set channel as high priority:
111 - const: stericsson,db8500-dma40
112 - const: stericsson,dma40
116 - items:
117 - description: DMA40 memory base
118 - items:
119 - description: DMA40 memory base
120 - description: LCPA memory base, deprecated, use eSRAM pool instead
124 reg-names:
126 - items:
127 - const: base
128 - items:
129 - const: base
130 - const: lcpa
134 maxItems: 1
137 maxItems: 1
140 $ref: /schemas/types.yaml#/definitions/phandle-array
141 description: A phandle array with inner size 1 (no arg cells).
142 First phandle is the LCPA (Logical Channel Parameter Address) memory.
143 Second phandle is the LCLA (Logical Channel Link base Address) memory.
146 maxItems: 1
148 memcpy-channels:
149 $ref: /schemas/types.yaml#/definitions/uint32-array
154 - "#dma-cells"
155 - compatible
156 - reg
157 - interrupts
158 - clocks
159 - sram
160 - memcpy-channels
165 - |
166 #include <dt-bindings/interrupt-controller/irq.h>
167 #include <dt-bindings/interrupt-controller/arm-gic.h>
168 #include <dt-bindings/mfd/dbx500-prcmu.h>
169 dma-controller@801c0000 {
170 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
172 reg-names = "base";
175 #dma-cells = <3>;
176 memcpy-channels = <56 57 58 59 60>;