Lines Matching +full:channel +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
50 * Implement support for Line-in capture on SB Live 24bit.
65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
94 #define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
107 #define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
108 #define INTE_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
126 #define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */
127 #define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */
128 #define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */
129 #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */
131 #define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */
133 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
134 /* Should be set to 1 when the EMU10K1 is */
136 #define CA0106_GPIO 0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */
137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
140 * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.
141 * bit 9 0 = Mute / 1 = Analog out.
142 * bit 10 0 = Line-in / 1 = Mic-in.
143 * bit 11 0 = ? / 1 = ?
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
145 * bit 13 0 = ? / 1 = ?
146 * bit 14 0 = Mute / 1 = Analog out
147 * bit 15 0 = ? / 1 = ?
153 * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin.
160 /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers …
171 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
183 /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */
196 /* 0x21 - 0x3f unused */
201 /* Start Playback [3:0] (one bit per channel)
202 * Start Capture [11:8] (one bit per channel)
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
204 * Playback mixer in enable [27:24] (one bit per channel)
205 * Playback mixer out enable [31:28] (one bit per channel)
208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
211 …tandard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Shield on all three…
217 * Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output
219 /* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Fr…
220 …standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM outpu…
222 #define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-…
223 #define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */
224 #define SPCS2 0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */
225 #define SPCS3 0x44 /* SPDIF output Channel Status 3 register. Unknown */
226 /* When Channel set to 0: */
235 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
236 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
237 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
238 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
241 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
242 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
243 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
246 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
247 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
248 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
249 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
251 /* When Channel set to 1: */
281 #define SPDIF_SELECT1 0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */
282 /* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE.
292 /* When Channel = 0:
293 * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit)
294 * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)
295 * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass)
297 /* When Channel = 1:
299 * SPDIF 1 User data [15:8]
306 * When Channel = 0: Bits the same as SPCS channel 0.
307 * When Channel = 1: Bits the same as SPCS channel 1.
308 * When Channel = 2:
312 #define CAPTURE_CACHE_DATA 0x50 /* 0x50-0x5f Recorded samples. */
315 #define CAPTURE_SOURCE_CHANNEL1 0x0f000000 /* 0 - SPDIF mixer output. */
316 #define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */
317 #define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */
319 …/* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to…
320 * Record source select for channel 0 [18:16]
321 * Record source select for channel 1 [22:20]
322 * Record source select for channel 2 [26:24]
323 * Record source select for channel 3 [30:28]
324 * 0 - SPDIF mixer output.
325 * 1 - i2s mixer output.
326 * 2 - SPDIF input.
327 * 3 - i2s input.
328 * 4 - AC97 capture.
329 * 5 - SRC output.
331 #define CAPTURE_VOLUME1 0x61 /* Capture volume per channel 0-3 */
332 #define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */
334 #define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 ou…
335 #define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to …
337 …ER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */
339 /* Channel_id's handle stereo channels. Channel X is a single mono channel */
341 /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
342 * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
343 * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
344 * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
345 * Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
346 * Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
347 * Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
348 * Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
353 /* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
354 * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
355 * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
356 * SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
357 * SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
358 * SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
359 * SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
360 * SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
365 * Invert SRC to SPDIF Mixer [7-0] (One bit per channel)
366 * Invert Host to SPDIF Mixer [15:8] (One bit per channel)
367 * SRC to SPDIF Mixer disable [23:16] (One bit per channel)
368 * Host to SPDIF Mixer disable [31:24] (One bit per channel)
370 #define PLAYBACK_VOLUME1 0x66 /* Playback SPDIF volume per channel. Set to the sa…
372 /* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */
385 #define PLAYBACK_VOLUME2 0x6a /* Playback Analog volume per channel. Does not eff…
393 /* unique channel identifier for midi->channel */
409 * SPDIF Locked [21] For SPDIF channel only.
410 * Valid Audio [22] For SPDIF channel only.
414 /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */
415 /* Sample rate output control register Channel=0
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
418 * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
421 * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
422 * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
423 * I2S output source select [18] (0=Audio from host, 1=Audio from SRC)
425 * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)
426 * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)
427 * I2S input mode [23] (0=Slave, 1=Master)
428 * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
429 * SPDIF output source select [26] (0=host, 1=SRC)
431 * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
432 * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
434 /* Sample rate output control register Channel=1
437 * I2S Input 1 volume Right [23:16]
438 * I2S Input 1 volume Left [31:24]
440 /* Sample rate output control register Channel=2
444 /* Sample rate output control register Channel=3
481 #define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */
506 #define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1
531 #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
533 #define PCM_REAR_CHANNEL 1
538 #define CONTROL_CENTER_LFE_CHANNEL 1
543 #define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */
547 #define SPI_RDA1_REG 1
556 #define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */
561 #define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */
562 #define SPI_PL_BIT_L_L (1<<5) /* left channel = left */
563 #define SPI_PL_BIT_L_R (2<<5) /* left channel = right */
564 #define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */
565 #define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */
566 #define SPI_PL_BIT_R_L (1<<7) /* right channel = left */
567 #define SPI_PL_BIT_R_R (2<<7) /* right channel = right */
568 #define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */
574 #define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */
578 #define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */
580 #define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */
582 #define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */
583 #define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */
584 #define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */
585 #define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */
588 #define SPI_MS_BIT (1<<5) /* master mode */
591 #define SPI_RATE_BIT_192 (1<<6)
597 /* They really do label the bit for the 4th channel "4" and not "3" */
602 #define SPI_DMUTE0_BIT (1<<3)
603 #define SPI_DMUTE1_BIT (1<<4)
604 #define SPI_DMUTE2_BIT (1<<5)
605 #define SPI_DMUTE4_BIT (1<<2)
611 #define SPI_PHASE0_BIT (1<<6)
612 #define SPI_PHASE1_BIT (1<<7)
613 #define SPI_PHASE2_BIT (1<<8)
614 #define SPI_PHASE4_BIT (1<<3)
617 #define SPI_PDWN_BIT (1<<2)
622 #define SPI_DACD0_BIT (1<<1)
623 #define SPI_DACD1_BIT (1<<2)
624 #define SPI_DACD2_BIT (1<<3)
625 #define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */
628 #define SPI_PWRDNALL_BIT (1<<4)
638 void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel);
652 int ac97; /* ac97 = 0 -> Select MIC, Line in, TAD in, AUX in.
653 ac97 = 1 -> Default to AC97 in. */
654 int gpio_type; /* gpio_type = 1 -> shared mic-in/line-in
655 gpio_type = 2 -> shared side-out/line-in. */
656 int i2c_adc; /* with i2c_adc=1, the driver adds some capture volume
657 controls, phone, mic, line-in and aux. */
658 u16 spi_dac; /* spi_dac = 0 -> no spi interface for DACs
659 spi_dac = 0x<front><rear><center-lfe><side>
660 -> specifies DAC id for each channel pair. */
663 // definition of the chip-specific record
683 u32 spdif_str_bits[4]; /* s/pdif out per-stream setup */