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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
[all …]
/freebsd/crypto/openssh/
H A Dnchan.c35 #include "openbsd-compat/sys-queue.h"
45 * SSH Protocol 1.5 aka New Channel Protocol
52 * 1.3: strict request-ack-protocol:
53 * CLOSE ->
54 * <- CLOSE_CONFIRM
57 * IEOF ->
58 * <- OCLOSE
59 * <- IEOF
60 * OCLOSE ->
61 * i.e. both sides have to close the channel
[all …]
H A Dchannels.h41 /* Definitions for channel types. */
45 #define SSH_CHANNEL_OPEN 4 /* normal open two-way channel */
50 #define SSH_CHANNEL_RPORT_LISTENER 11 /* Listening to a R-style port */
58 #define SSH_CHANNEL_RUNIX_LISTENER 19 /* Listening to a R-style domain socket. */
59 #define SSH_CHANNEL_MUX_PROXY 20 /* proxy channel for mux-client */
64 #define CHANNEL_CANCEL_PORT_STATIC -1
67 #define CHANNEL_NONBLOCK_LEAVE 0 /* don't modify non-blocking state */
68 #define CHANNEL_NONBLOCK_SET 1 /* set non-blocking state */
69 #define CHANNEL_NONBLOCK_STDIO 2 /* set non-blocking and restore on close */
71 /* c->restore_block mask flags */
[all …]
/freebsd/contrib/wpa/src/drivers/
H A Ddriver_macsec_qca.c3 * Copyright (c) 2005-2009, Jouni Malinen <j@w1.fi>
5 * Copyright (c) 2013-2014, Qualcomm Atheros, Inc.
91 wpa_printf(MSG_INFO, "%s: secy_id=%d", __func__, drv->secy_id); in __macsec_drv_init()
94 ret = nss_macsec_secy_en_set(drv->secy_id, true); in __macsec_drv_init()
98 ret = nss_macsec_secy_sc_sa_mapping_mode_set(drv->secy_id, in __macsec_drv_init()
109 ret = nss_macsec_secy_rx_ctl_filt_set(drv->secy_id, 0, &rx_ctl_filt); in __macsec_drv_init()
118 ret = nss_macsec_secy_tx_ctl_filt_set(drv->secy_id, 0, &tx_ctl_filt); in __macsec_drv_init()
126 nss_macsec_secy_en_set(drv->secy_id, false); in __macsec_drv_deinit()
127 nss_macsec_secy_rx_sc_del_all(drv->secy_id); in __macsec_drv_deinit()
128 nss_macsec_secy_tx_sc_del_all(drv->secy_id); in __macsec_drv_deinit()
[all …]
/freebsd/contrib/ntp/libntp/lib/isc/
H A Dlog.c2 * Copyright (C) 2004-2007, 2009, 2011, 2012 Internet Systems Consortium, Inc. ("ISC")
3 * Copyright (C) 1999-2003 Internet Software Consortium.
62 * This is the structure that holds each named channel. A simple linked
63 * list chains all of the channels together, so an individual channel is
93 isc_logchannel_t * channel; member
111 * about where messages are actually supposed to be sent -- the information
162 * Used when ISC_LOG_PRINTLEVEL is enabled for a channel.
214 * because its channel member is pointed to a channel that is created
229 const isc_logmodule_t *module, isc_logchannel_t *channel);
235 greatest_version(isc_logchannel_t *channel, int *greatest);
[all …]
/freebsd/contrib/wpa/src/ap/
H A Ddfs.c2 * DFS - Dynamic Frequency Selection
3 * Copyright (c) 2002-2013, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2013-2017, Qualcomm Atheros, Inc.
25 DFS_AVAILABLE, /* non-radar or radar-available */
26 DFS_NO_CAC_YET, /* radar-not-yet-available */
38 return (iface->drv_flags2 & WPA_DRIVER_FLAGS2_RADAR_BACKGROUND) && in dfs_use_radar_background()
39 iface->conf->enable_background_radar; in dfs_use_radar_background()
49 if (iface->conf->ieee80211n && iface->conf->secondary_channel) in dfs_get_used_n_chans()
52 if (iface->conf->ieee80211ac || iface->conf->ieee80211ax) { in dfs_get_used_n_chans()
53 switch (hostapd_get_oper_chwidth(iface->conf)) { in dfs_get_used_n_chans()
[all …]
/freebsd/sys/dev/pwm/
H A Dpwm_backlight.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 pwm_channel_t channel; member
78 { "pwm-backlight", 1 },
86 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in pwm_backlight_probe()
103 rv = pwm_get_by_ofw_propidx(dev, node, "pwms", 0, &sc->channel); in pwm_backlight_attach()
105 device_printf(dev, "Cannot map pwm channel %d\n", rv); in pwm_backlight_attach()
109 if (regulator_get_by_ofw_property(dev, 0, "power-supply", in pwm_backlight_attach()
110 &sc->power_supply) != 0) { in pwm_backlight_attach()
111 device_printf(dev, "No power-supply property\n"); in pwm_backlight_attach()
[all …]
/freebsd/sys/contrib/openzfs/man/man5/
H A Dvdev_id.conf.51 .\" SPDX-License-Identifier: CDDL-1.0
35 .Bl -tag -width "-h"
42 A defined alias takes precedence over a topology-derived name, but the
50 .Pa /dev/disk/by-vdev .
57 .It Sy channel [ Ns Ar pci_slot ] Ar port Ar name
58 Maps a physical path to a channel name (typically representing a single
63 .Pa /dev/by-enclosure
75 .Pa /dev/by-enclosure/ Ns Ao Ar prefix Ac Ns - Ns Ao Ar channel Ac Ns Aq Ar num
80 .It Sy slot Ar prefix Ar new Op Ar channel
84 .Ar channel
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dadi,ad5770r.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandru Tachici <alexandru.tachici@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD5770R.pdf
21 - adi,ad5770r
26 avdd-supply:
31 iovdd-supply:
35 vref-supply:
41 adi,external-resistor:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
H A Dadi,ad7173.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ceclan Dumitru <dumitru.ceclan@analog.com>
15 The AD717x family offer a complete integrated Sigma-Delta ADC solution which
16 can be used in high precision, low noise single channel applications
18 (Factory Automation PLC Input modules). The Sigma-Delta ADC is intended
23 The AD411X family encompasses a series of low power, low noise, 24-bit,
24 sigma-delta analog-to-digital converters that offer a versatile range of
26 fully differential/single-ended and bipolar voltage inputs.
[all …]
H A Dqcom,pm8018-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
29 xoadc-ref-supply:
[all …]
H A Dqcom,pm8xxx-xoadc.txt8 - compatible: should be one of:
9 "qcom,pm8018-adc"
10 "qcom,pm8038-adc"
11 "qcom,pm8058-adc"
12 "qcom,pm8921-adc"
14 - reg: should contain the ADC base address in the PMIC, typically
17 - xoadc-ref-supply: should reference a regulator that can supply
22 iio-bindings.txt for more details, but notice that this particular
24 identifying each ADC channel:
26 - #address-cells: should be set to <2>, the first cell is the
[all …]
/freebsd/contrib/wpa/src/common/
H A Dhw_features_common.c3 * Copyright (c) 2002-2013, Jouni Malinen <j@w1.fi>
30 for (i = 0; i < mode->num_channels; i++) { in hw_get_channel_chan()
31 struct hostapd_channel_data *ch = &mode->channels[i]; in hw_get_channel_chan()
32 if (ch->chan == chan) { in hw_get_channel_chan()
34 *freq = ch->freq; in hw_get_channel_chan()
48 for (i = 0; i < mode->num_channels; i++) { in hw_mode_get_channel()
49 struct hostapd_channel_data *ch = &mode->channels[i]; in hw_mode_get_channel()
51 if (ch->freq == freq) { in hw_mode_get_channel()
53 *chan = ch->chan; in hw_mode_get_channel()
78 if (curr_mode->mode != mode) in hw_get_channel_freq()
[all …]
/freebsd/crypto/openssl/crypto/
H A Dtrace.c2 * Copyright 2019-2023 The OpenSSL Project Authors. All Rights Reserved.
29 /*-
30 * INTERNAL TRACE CHANNEL IMPLEMENTATION
33 * BIO sink object, also called the trace channel. Instead of a BIO object,
35 * internal trace channel is attached, which simply calls the registered
41 static long trace_ctrl(BIO *channel, int cmd, long argl, void *argp);
65 static int trace_write(BIO *channel, in trace_write() argument
68 struct trace_data_st *ctx = BIO_get_data(channel); in trace_write()
69 size_t cnt = ctx->callback(buf, num, ctx->category, OSSL_TRACE_CTRL_WRITE, in trace_write()
70 ctx->data); in trace_write()
[all …]
/freebsd/contrib/wpa/wpa_supplicant/
H A Doffchannel.c2 * wpa_supplicant - Off-channel Action frame TX/RX
3 * Copyright (c) 2009-2010, Atheros Communications
26 if (ether_addr_equal(src, wpa_s->own_addr)) { in wpas_get_tx_interface()
28 if (wpa_s->p2p_mgmt && wpa_s != wpa_s->parent && in wpas_get_tx_interface()
29 wpa_s->parent->ap_iface && in wpas_get_tx_interface()
30 ether_addr_equal(wpa_s->parent->own_addr, in wpas_get_tx_interface()
31 wpa_s->own_addr) && in wpas_get_tx_interface()
32 wpabuf_len(wpa_s->pending_action_tx) >= 2 && in wpas_get_tx_interface()
33 *wpabuf_head_u8(wpa_s->pending_action_tx) != in wpas_get_tx_interface()
37 * the GO interface, make sure non-Public Action frames in wpas_get_tx_interface()
[all …]
/freebsd/lib/libpmc/
H A Dpmc.corei7uc.344 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
92 Configure the PMC to count the number of de-asserted to asserted
107 .Bl -tag -width indent
420 Uncore cycles all the entries in the DRAM channel 0 medium or low priority
424 Uncore cycles all the entries in the DRAM channel 1 medium or low priority
[all …]
/freebsd/sys/amd64/vmm/io/
H A Dvatpit.c1 /*-
52 #define VATPIT_LOCK(vatpit) mtx_lock_spin(&((vatpit)->mtx))
53 #define VATPIT_UNLOCK(vatpit) mtx_unlock_spin(&((vatpit)->mtx))
54 #define VATPIT_LOCKED(vatpit) mtx_owned(&((vatpit)->mtx))
80 struct channel { struct
102 struct channel channel[3]; argument
108 vatpit_delta_ticks(struct vatpit *vatpit, struct channel *c) in vatpit_delta_ticks()
114 bintime_sub(&delta, &c->now_bt); in vatpit_delta_ticks()
117 result += delta.frac / vatpit->freq_bt.frac; in vatpit_delta_ticks()
123 vatpit_get_out(struct vatpit *vatpit, int channel) in vatpit_get_out() argument
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_edma.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #define DMA_DCHPRI3 0x100 /* Channel n Priority */
48 #define DMA_DCHPRI2 0x101 /* Channel n Priority */
49 #define DMA_DCHPRI1 0x102 /* Channel n Priority */
50 #define DMA_DCHPRI0 0x103 /* Channel n Priority */
51 #define DMA_DCHPRI7 0x104 /* Channel n Priority */
52 #define DMA_DCHPRI6 0x105 /* Channel n Priority */
53 #define DMA_DCHPRI5 0x106 /* Channel n Priority */
54 #define DMA_DCHPRI4 0x107 /* Channel n Priority */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.0
[all...]
/freebsd/contrib/wpa/src/p2p/
H A Dp2p_utils.c2 * P2P - generic helper functions
18 * p2p_random - Generate random string for SSID and passphrase
21 * Returns: 0 on success, -1 on failure
24 * 'A'-'Z', 'a'-'z', '0'-'9'.
30 u8 letters = 'Z' - 'A' + 1; in p2p_random()
34 return -1; in p2p_random()
35 /* Character set: 'A'-'Z', 'a'-'z', '0'-'9' */ in p2p_random()
42 buf[i] = 'a' + (val - letters); in p2p_random()
44 buf[i] = '0' + (val - 2 * letters); in p2p_random()
52 * p2p_channel_to_freq - Convert channel info to frequency
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
/freebsd/share/man/man9/
H A Dpwmbus.941 .Fn PWMBUS_CHANNEL_CONFIG "device_t bus" "u_int channel" "u_int period" "u_int duty"
45 .Fn PWMBUS_CHANNEL_ENABLE "device_t bus" "u_int channel" "bool enable"
47 .Fn PWMBUS_CHANNEL_GET_CONFIG "device_t bus" "u_int channel" "u_int *period" "u_int *duty"
49 .Fn PWMBUS_CHANNEL_GET_FLAGS "device_t bus" "u_int channel" "uint32_t *flags"
51 .Fn PWMBUS_CHANNEL_IS_ENABLED "device_t bus" "u_int channel" "bool *enabled"
53 .Fn PWMBUS_CHANNEL_SET_FLAGS "device_t bus" "u_int channel" "uint32_t flags"
55 The PWMBUS (Pulse-Width Modulation) interface allows a device driver to
63 argument is the duration in nanoseconds of one complete on-off cycle, and the
68 Channel numbers count up from zero.
71 In such cases, changing the period or duty cycle of any one channel may affect
[all …]
/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]

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