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Searched full:cclk (Results 1 – 25 of 56) sorted by relevance

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/linux/drivers/clk/ti/
H A Dcomposite.c116 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); in _register_composite() local
126 if (!cclk->comp_nodes[i]) in _register_composite()
129 comp = _lookup_component(cclk->comp_nodes[i]); in _register_composite()
132 cclk->comp_nodes[i]->name, node); in _register_composite()
139 if (cclk->comp_clks[comp->type] != NULL) { in _register_composite()
145 cclk->comp_clks[comp->type] = comp; in _register_composite()
148 cclk->comp_nodes[i] = NULL; in _register_composite()
153 comp = cclk->comp_clks[i]; in _register_composite()
171 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), in _register_composite()
173 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER), in _register_composite()
[all …]
/linux/sound/soc/samsung/
H A Dpcm.c113 * @cclk: the SCLK_AUDIO (audio-bus) clock pointer
128 struct clk *cclk; member
288 clk = pcm->cclk; in s3c_pcm_hw_params()
421 if (clk_get_rate(pcm->cclk) != freq) in s3c_pcm_set_sysclk()
422 clk_set_rate(pcm->cclk, freq); in s3c_pcm_set_sysclk()
520 pcm->cclk = devm_clk_get(&pdev->dev, "audio-bus"); in s3c_pcm_dev_probe()
521 if (IS_ERR(pcm->cclk)) { in s3c_pcm_dev_probe()
523 return PTR_ERR(pcm->cclk); in s3c_pcm_dev_probe()
525 ret = clk_prepare_enable(pcm->cclk); in s3c_pcm_dev_probe()
578 clk_disable_unprepare(pcm->cclk); in s3c_pcm_dev_probe()
[all …]
/linux/drivers/clk/sprd/
H A Dcommon.c27 struct sprd_clk_common *cclk; in sprd_clk_set_regmap() local
30 cclk = desc->clk_clks[i]; in sprd_clk_set_regmap()
31 if (!cclk) in sprd_clk_set_regmap()
34 cclk->regmap = regmap; in sprd_clk_set_regmap()
/linux/drivers/net/pcs/
H A Dpcs-xpcs-plat.c33 struct clk *cclk; member
283 pxpcs->cclk = devm_clk_get_optional(dev, "csr"); in xpcs_plat_init_clk()
284 if (IS_ERR(pxpcs->cclk)) in xpcs_plat_init_clk()
285 return dev_err_probe(dev, PTR_ERR(pxpcs->cclk), in xpcs_plat_init_clk()
408 clk_disable_unprepare(pxpcs->cclk); in xpcs_plat_pm_runtime_suspend()
417 return clk_prepare_enable(pxpcs->cclk); in xpcs_plat_pm_runtime_resume()
/linux/drivers/net/can/m_can/
H A Dm_can_platform.c143 mcan_class->can.clock.freq = clk_get_rate(mcan_class->cclk); in m_can_plat_probe()
192 clk_disable_unprepare(mcan_class->cclk); in m_can_runtime_suspend()
208 err = clk_prepare_enable(mcan_class->cclk); in m_can_runtime_resume()
H A Dtcan4x5x-core.c437 mcan_class->cclk = devm_clk_get(mcan_class->dev, "cclk"); in tcan4x5x_can_probe()
438 if (IS_ERR(mcan_class->cclk)) { in tcan4x5x_can_probe()
442 freq = clk_get_rate(mcan_class->cclk); in tcan4x5x_can_probe()
H A Dm_can.h88 struct clk *cclk; member
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,adc12138.yaml49 For less ADC accuracy and/or slower CCLK frequencies this value may be
80 clocks = <&cclk>;
/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_common.h198 u32 cclk; /* Core Clock (KHz) */ member
311 return adapter->params.vpd.cclk / 1000; in core_ticks_per_usec()
317 return (us * adapter->params.vpd.cclk) / 1000; in us_to_core_ticks()
323 return (ticks * 1000) / adapter->params.vpd.cclk; in core_ticks_to_us()
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c307 * cclk = mclk / (2 * clkdiv) in mmci_sdmmc_set_clkreg()
313 host->cclk = host->mclk; in mmci_sdmmc_set_clkreg()
318 host->cclk = host->mclk / (2 * clk); in mmci_sdmmc_set_clkreg()
327 host->cclk = host->mclk / (2 * clk); in mmci_sdmmc_set_clkreg()
332 host->mmc->actual_clock = host->cclk; in mmci_sdmmc_set_clkreg()
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62-mcu.dtsi161 clock-names = "hclk", "cclk";
173 clock-names = "hclk", "cclk";
/linux/drivers/scsi/csiostor/
H A Dcsio_hw.h265 uint32_t cclk; member
582 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk; in csio_core_ticks_to_us()
588 return (us * hw->vpd.cclk) / 1000; in csio_us_to_core_ticks()
/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi386 clock-names = "hclk", "cclk";
402 clock-names = "hclk", "cclk";
418 clock-names = "hclk", "cclk";
434 clock-names = "hclk", "cclk";
450 clock-names = "hclk", "cclk";
466 clock-names = "hclk", "cclk";
H A Dlan966x.dtsi485 clock-names = "hclk", "cclk";
500 clock-names = "hclk", "cclk";
/linux/drivers/clk/tegra/
H A DMakefile17 obj-y += clk-tegra-super-cclk.o
H A Dclk-tegra20.c436 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
708 /* CCLK */ in tegra20_super_clk_init()
709 clk = tegra_clk_register_super_cclk("cclk", cclk_parents, in tegra20_super_clk_init()
716 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); in tegra20_super_clk_init()
H A Dclk-tegra-super-cclk.c81 * Switch parent to PLLP for all CCLK rates that are suitable for PLLP. in cclk_super_determine_rate()
/linux/drivers/clk/ingenic/
H A Djz4770-cgu.c151 "cclk", CGU_CLK_DIV,
195 .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
H A Djz4740-cgu.c104 "cclk", CGU_CLK_DIV,
H A Djz4725b-cgu.c89 "cclk", CGU_CLK_DIV,
H A Djz4755-cgu.c95 "cclk", CGU_CLK_DIV,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi36 clock-names = "hclk", "cclk";
/linux/arch/arm/mach-sa1100/include/mach/
H A Dassabet.h97 #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml33 st,fmc2-ebi-cs-cclk-enable:
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c604 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", in vangogh_print_legacy_clk_levels()
701 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n", in vangogh_print_clk_levels()
2036 …dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allow… in vangogh_od_edit_dpm_table()
2043 …dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum al… in vangogh_od_edit_dpm_table()
2126 dev_err(smu->adev->dev, "Set hard min cclk failed!"); in vangogh_od_edit_dpm_table()
2135 dev_err(smu->adev->dev, "Set soft max cclk failed!"); in vangogh_od_edit_dpm_table()

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