1a3667aaeSNaresh Kumar Inna /*
2a3667aaeSNaresh Kumar Inna * This file is part of the Chelsio FCoE driver for Linux.
3a3667aaeSNaresh Kumar Inna *
4a3667aaeSNaresh Kumar Inna * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5a3667aaeSNaresh Kumar Inna *
6a3667aaeSNaresh Kumar Inna * This software is available to you under a choice of one of two
7a3667aaeSNaresh Kumar Inna * licenses. You may choose to be licensed under the terms of the GNU
8a3667aaeSNaresh Kumar Inna * General Public License (GPL) Version 2, available from the file
9a3667aaeSNaresh Kumar Inna * COPYING in the main directory of this source tree, or the
10a3667aaeSNaresh Kumar Inna * OpenIB.org BSD license below:
11a3667aaeSNaresh Kumar Inna *
12a3667aaeSNaresh Kumar Inna * Redistribution and use in source and binary forms, with or
13a3667aaeSNaresh Kumar Inna * without modification, are permitted provided that the following
14a3667aaeSNaresh Kumar Inna * conditions are met:
15a3667aaeSNaresh Kumar Inna *
16a3667aaeSNaresh Kumar Inna * - Redistributions of source code must retain the above
17a3667aaeSNaresh Kumar Inna * copyright notice, this list of conditions and the following
18a3667aaeSNaresh Kumar Inna * disclaimer.
19a3667aaeSNaresh Kumar Inna *
20a3667aaeSNaresh Kumar Inna * - Redistributions in binary form must reproduce the above
21a3667aaeSNaresh Kumar Inna * copyright notice, this list of conditions and the following
22a3667aaeSNaresh Kumar Inna * disclaimer in the documentation and/or other materials
23a3667aaeSNaresh Kumar Inna * provided with the distribution.
24a3667aaeSNaresh Kumar Inna *
25a3667aaeSNaresh Kumar Inna * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26a3667aaeSNaresh Kumar Inna * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27a3667aaeSNaresh Kumar Inna * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28a3667aaeSNaresh Kumar Inna * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29a3667aaeSNaresh Kumar Inna * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30a3667aaeSNaresh Kumar Inna * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31a3667aaeSNaresh Kumar Inna * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32a3667aaeSNaresh Kumar Inna * SOFTWARE.
33a3667aaeSNaresh Kumar Inna */
34a3667aaeSNaresh Kumar Inna
35a3667aaeSNaresh Kumar Inna #ifndef __CSIO_HW_H__
36a3667aaeSNaresh Kumar Inna #define __CSIO_HW_H__
37a3667aaeSNaresh Kumar Inna
38a3667aaeSNaresh Kumar Inna #include <linux/kernel.h>
39a3667aaeSNaresh Kumar Inna #include <linux/pci.h>
40a3667aaeSNaresh Kumar Inna #include <linux/device.h>
41a3667aaeSNaresh Kumar Inna #include <linux/workqueue.h>
42a3667aaeSNaresh Kumar Inna #include <linux/compiler.h>
43a3667aaeSNaresh Kumar Inna #include <linux/cdev.h>
44a3667aaeSNaresh Kumar Inna #include <linux/list.h>
45a3667aaeSNaresh Kumar Inna #include <linux/mempool.h>
46a3667aaeSNaresh Kumar Inna #include <linux/io.h>
47a3667aaeSNaresh Kumar Inna #include <linux/spinlock_types.h>
48a3667aaeSNaresh Kumar Inna #include <scsi/scsi_device.h>
49a3667aaeSNaresh Kumar Inna #include <scsi/scsi_transport_fc.h>
50a3667aaeSNaresh Kumar Inna
51216ce69cSPraveen Madhavan #include "t4_hw.h"
527cc16380SArvind Bhushan #include "csio_hw_chip.h"
53a3667aaeSNaresh Kumar Inna #include "csio_wr.h"
54a3667aaeSNaresh Kumar Inna #include "csio_mb.h"
55a3667aaeSNaresh Kumar Inna #include "csio_scsi.h"
56a3667aaeSNaresh Kumar Inna #include "csio_defs.h"
57a3667aaeSNaresh Kumar Inna #include "t4_regs.h"
58a3667aaeSNaresh Kumar Inna #include "t4_msg.h"
59a3667aaeSNaresh Kumar Inna
60a3667aaeSNaresh Kumar Inna /*
61a3667aaeSNaresh Kumar Inna * An error value used by host. Should not clash with FW defined return values.
62a3667aaeSNaresh Kumar Inna */
63a3667aaeSNaresh Kumar Inna #define FW_HOSTERROR 255
64a3667aaeSNaresh Kumar Inna
65a3667aaeSNaresh Kumar Inna #define CSIO_HW_NAME "Chelsio FCoE Adapter"
66a3667aaeSNaresh Kumar Inna #define CSIO_MAX_PFN 8
67a3667aaeSNaresh Kumar Inna #define CSIO_MAX_PPORTS 4
68a3667aaeSNaresh Kumar Inna
69a3667aaeSNaresh Kumar Inna #define CSIO_MAX_LUN 0xFFFF
70a3667aaeSNaresh Kumar Inna #define CSIO_MAX_QUEUE 2048
71a3667aaeSNaresh Kumar Inna #define CSIO_MAX_CMD_PER_LUN 32
72a3667aaeSNaresh Kumar Inna #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
73a3667aaeSNaresh Kumar Inna #define CSIO_MAX_SECTOR_SIZE 128
7496e6c633SVarun Prakash #define CSIO_MIN_T6_FW 0x01102D00 /* FW 1.16.45.0 */
75a3667aaeSNaresh Kumar Inna
76a3667aaeSNaresh Kumar Inna /* Interrupts */
77a3667aaeSNaresh Kumar Inna #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
78a3667aaeSNaresh Kumar Inna * (Forward intr iq + fw iq) */
79a3667aaeSNaresh Kumar Inna #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
80a3667aaeSNaresh Kumar Inna #define CSIO_MAX_SCSI_CPU 128
81a3667aaeSNaresh Kumar Inna #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
82a3667aaeSNaresh Kumar Inna #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
83a3667aaeSNaresh Kumar Inna
84a3667aaeSNaresh Kumar Inna /* Queues */
85a3667aaeSNaresh Kumar Inna enum {
86a3667aaeSNaresh Kumar Inna CSIO_INTR_WRSIZE = 128,
87a3667aaeSNaresh Kumar Inna CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
88a3667aaeSNaresh Kumar Inna CSIO_FWEVT_WRSIZE = 128,
89a3667aaeSNaresh Kumar Inna CSIO_FWEVT_IQLEN = 128,
90a3667aaeSNaresh Kumar Inna CSIO_FWEVT_FLBUFS = 64,
91a3667aaeSNaresh Kumar Inna CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
92a3667aaeSNaresh Kumar Inna CSIO_HW_NIQ = 1,
93a3667aaeSNaresh Kumar Inna CSIO_HW_NFLQ = 1,
94a3667aaeSNaresh Kumar Inna CSIO_HW_NEQ = 1,
95a3667aaeSNaresh Kumar Inna CSIO_HW_NINTXQ = 1,
96a3667aaeSNaresh Kumar Inna };
97a3667aaeSNaresh Kumar Inna
98a3667aaeSNaresh Kumar Inna struct csio_msix_entries {
99a3667aaeSNaresh Kumar Inna void *dev_id; /* Priv object associated w/ this msix*/
100a3667aaeSNaresh Kumar Inna char desc[24]; /* Description of this vector */
101a3667aaeSNaresh Kumar Inna };
102a3667aaeSNaresh Kumar Inna
103a3667aaeSNaresh Kumar Inna struct csio_scsi_qset {
104a3667aaeSNaresh Kumar Inna int iq_idx; /* Ingress index */
105a3667aaeSNaresh Kumar Inna int eq_idx; /* Egress index */
106a3667aaeSNaresh Kumar Inna uint32_t intr_idx; /* MSIX Vector index */
107a3667aaeSNaresh Kumar Inna };
108a3667aaeSNaresh Kumar Inna
109a3667aaeSNaresh Kumar Inna struct csio_scsi_cpu_info {
110a3667aaeSNaresh Kumar Inna int16_t max_cpus;
111a3667aaeSNaresh Kumar Inna };
112a3667aaeSNaresh Kumar Inna
113a3667aaeSNaresh Kumar Inna extern int csio_dbg_level;
114a3667aaeSNaresh Kumar Inna extern unsigned int csio_port_mask;
115a3667aaeSNaresh Kumar Inna extern int csio_msi;
116a3667aaeSNaresh Kumar Inna
117a3667aaeSNaresh Kumar Inna #define CSIO_VENDOR_ID 0x1425
118a3667aaeSNaresh Kumar Inna #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
119a3667aaeSNaresh Kumar Inna #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
120a3667aaeSNaresh Kumar Inna
1210d804338SHariprasad Shenai #define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
1220d804338SHariprasad Shenai EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
1230d804338SHariprasad Shenai PM_TX_F | PM_RX_F | ULP_RX_F | \
1240d804338SHariprasad Shenai CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
125a3667aaeSNaresh Kumar Inna
126a3667aaeSNaresh Kumar Inna /*
127a3667aaeSNaresh Kumar Inna * Hard parameters used to initialize the card in the absence of a
128a3667aaeSNaresh Kumar Inna * configuration file.
129a3667aaeSNaresh Kumar Inna */
130a3667aaeSNaresh Kumar Inna enum {
131a3667aaeSNaresh Kumar Inna /* General */
132a3667aaeSNaresh Kumar Inna CSIO_SGE_DBFIFO_INT_THRESH = 10,
133a3667aaeSNaresh Kumar Inna
134a3667aaeSNaresh Kumar Inna CSIO_SGE_RX_DMA_OFFSET = 2,
135a3667aaeSNaresh Kumar Inna
136a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE1 = 65536,
137a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE2 = 1536,
138a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE3 = 9024,
139a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE4 = 9216,
140a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE5 = 2048,
141a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE6 = 128,
142a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE7 = 8192,
143a3667aaeSNaresh Kumar Inna CSIO_SGE_FLBUF_SIZE8 = 16384,
144a3667aaeSNaresh Kumar Inna
145a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_0 = 5,
146a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_1 = 10,
147a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_2 = 20,
148a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_3 = 50,
149a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_4 = 100,
150a3667aaeSNaresh Kumar Inna CSIO_SGE_TIMER_VAL_5 = 200,
151a3667aaeSNaresh Kumar Inna
152a3667aaeSNaresh Kumar Inna CSIO_SGE_INT_CNT_VAL_0 = 1,
153a3667aaeSNaresh Kumar Inna CSIO_SGE_INT_CNT_VAL_1 = 4,
154a3667aaeSNaresh Kumar Inna CSIO_SGE_INT_CNT_VAL_2 = 8,
155a3667aaeSNaresh Kumar Inna CSIO_SGE_INT_CNT_VAL_3 = 16,
156a3667aaeSNaresh Kumar Inna };
157a3667aaeSNaresh Kumar Inna
158a3667aaeSNaresh Kumar Inna /* Slowpath events */
159a3667aaeSNaresh Kumar Inna enum csio_evt {
160a3667aaeSNaresh Kumar Inna CSIO_EVT_FW = 0, /* FW event */
161a3667aaeSNaresh Kumar Inna CSIO_EVT_MBX, /* MBX event */
162a3667aaeSNaresh Kumar Inna CSIO_EVT_SCN, /* State change notification */
163a3667aaeSNaresh Kumar Inna CSIO_EVT_DEV_LOSS, /* Device loss event */
164a3667aaeSNaresh Kumar Inna CSIO_EVT_MAX, /* Max supported event */
165a3667aaeSNaresh Kumar Inna };
166a3667aaeSNaresh Kumar Inna
167a3667aaeSNaresh Kumar Inna #define CSIO_EVT_MSG_SIZE 512
168a3667aaeSNaresh Kumar Inna #define CSIO_EVTQ_SIZE 512
169a3667aaeSNaresh Kumar Inna
170a3667aaeSNaresh Kumar Inna /* Event msg */
171a3667aaeSNaresh Kumar Inna struct csio_evt_msg {
172a3667aaeSNaresh Kumar Inna struct list_head list; /* evt queue*/
173a3667aaeSNaresh Kumar Inna enum csio_evt type;
174a3667aaeSNaresh Kumar Inna uint8_t data[CSIO_EVT_MSG_SIZE];
175a3667aaeSNaresh Kumar Inna };
176a3667aaeSNaresh Kumar Inna
177a3667aaeSNaresh Kumar Inna enum {
178a3667aaeSNaresh Kumar Inna SERNUM_LEN = 16, /* Serial # length */
179a3667aaeSNaresh Kumar Inna EC_LEN = 16, /* E/C length */
180a3667aaeSNaresh Kumar Inna ID_LEN = 16, /* ID length */
181a3667aaeSNaresh Kumar Inna };
182a3667aaeSNaresh Kumar Inna
183a3667aaeSNaresh Kumar Inna enum {
184a3667aaeSNaresh Kumar Inna SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
185a3667aaeSNaresh Kumar Inna };
186a3667aaeSNaresh Kumar Inna
187a3667aaeSNaresh Kumar Inna /* serial flash and firmware constants */
188a3667aaeSNaresh Kumar Inna enum {
189a3667aaeSNaresh Kumar Inna SF_ATTEMPTS = 10, /* max retries for SF operations */
190a3667aaeSNaresh Kumar Inna
191a3667aaeSNaresh Kumar Inna /* flash command opcodes */
192a3667aaeSNaresh Kumar Inna SF_PROG_PAGE = 2, /* program page */
193a3667aaeSNaresh Kumar Inna SF_WR_DISABLE = 4, /* disable writes */
194a3667aaeSNaresh Kumar Inna SF_RD_STATUS = 5, /* read status register */
195a3667aaeSNaresh Kumar Inna SF_WR_ENABLE = 6, /* enable writes */
196a3667aaeSNaresh Kumar Inna SF_RD_DATA_FAST = 0xb, /* read flash */
197a3667aaeSNaresh Kumar Inna SF_RD_ID = 0x9f, /* read ID */
198a3667aaeSNaresh Kumar Inna SF_ERASE_SECTOR = 0xd8, /* erase sector */
199a3667aaeSNaresh Kumar Inna };
200a3667aaeSNaresh Kumar Inna
201a3667aaeSNaresh Kumar Inna /* Management module */
202a3667aaeSNaresh Kumar Inna enum {
203a3667aaeSNaresh Kumar Inna CSIO_MGMT_EQ_WRSIZE = 512,
204a3667aaeSNaresh Kumar Inna CSIO_MGMT_IQ_WRSIZE = 128,
205a3667aaeSNaresh Kumar Inna CSIO_MGMT_EQLEN = 64,
206a3667aaeSNaresh Kumar Inna CSIO_MGMT_IQLEN = 64,
207a3667aaeSNaresh Kumar Inna };
208a3667aaeSNaresh Kumar Inna
209a3667aaeSNaresh Kumar Inna #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
210a3667aaeSNaresh Kumar Inna #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
211a3667aaeSNaresh Kumar Inna
212a3667aaeSNaresh Kumar Inna /* mgmt module stats */
213a3667aaeSNaresh Kumar Inna struct csio_mgmtm_stats {
214a3667aaeSNaresh Kumar Inna uint32_t n_abort_req; /* Total abort request */
215a3667aaeSNaresh Kumar Inna uint32_t n_abort_rsp; /* Total abort response */
216a3667aaeSNaresh Kumar Inna uint32_t n_close_req; /* Total close request */
217a3667aaeSNaresh Kumar Inna uint32_t n_close_rsp; /* Total close response */
218a3667aaeSNaresh Kumar Inna uint32_t n_err; /* Total Errors */
219a3667aaeSNaresh Kumar Inna uint32_t n_drop; /* Total request dropped */
220a3667aaeSNaresh Kumar Inna uint32_t n_active; /* Count of active_q */
221a3667aaeSNaresh Kumar Inna uint32_t n_cbfn; /* Count of cbfn_q */
222a3667aaeSNaresh Kumar Inna };
223a3667aaeSNaresh Kumar Inna
224a3667aaeSNaresh Kumar Inna /* MGMT module */
225a3667aaeSNaresh Kumar Inna struct csio_mgmtm {
226a3667aaeSNaresh Kumar Inna struct csio_hw *hw; /* Pointer to HW moduel */
227a3667aaeSNaresh Kumar Inna int eq_idx; /* Egress queue index */
228a3667aaeSNaresh Kumar Inna int iq_idx; /* Ingress queue index */
229a3667aaeSNaresh Kumar Inna int msi_vec; /* MSI vector */
230a3667aaeSNaresh Kumar Inna struct list_head active_q; /* Outstanding ELS/CT */
231a3667aaeSNaresh Kumar Inna struct list_head abort_q; /* Outstanding abort req */
232a3667aaeSNaresh Kumar Inna struct list_head cbfn_q; /* Completion queue */
233a3667aaeSNaresh Kumar Inna struct list_head mgmt_req_freelist; /* Free poll of reqs */
234a3667aaeSNaresh Kumar Inna /* ELSCT request freelist*/
235a3667aaeSNaresh Kumar Inna struct timer_list mgmt_timer; /* MGMT timer */
236a3667aaeSNaresh Kumar Inna struct csio_mgmtm_stats stats; /* ELS/CT stats */
237a3667aaeSNaresh Kumar Inna };
238a3667aaeSNaresh Kumar Inna
239a3667aaeSNaresh Kumar Inna struct csio_adap_desc {
240a3667aaeSNaresh Kumar Inna char model_no[16];
241a3667aaeSNaresh Kumar Inna char description[32];
242a3667aaeSNaresh Kumar Inna };
243a3667aaeSNaresh Kumar Inna
244a3667aaeSNaresh Kumar Inna struct pci_params {
245a3667aaeSNaresh Kumar Inna uint16_t vendor_id;
246a3667aaeSNaresh Kumar Inna uint16_t device_id;
2477cc16380SArvind Bhushan int vpd_cap_addr;
248a3667aaeSNaresh Kumar Inna uint16_t speed;
249a3667aaeSNaresh Kumar Inna uint8_t width;
250a3667aaeSNaresh Kumar Inna };
251a3667aaeSNaresh Kumar Inna
252a3667aaeSNaresh Kumar Inna /* User configurable hw parameters */
253a3667aaeSNaresh Kumar Inna struct csio_hw_params {
254a3667aaeSNaresh Kumar Inna uint32_t sf_size; /* serial flash
255a3667aaeSNaresh Kumar Inna * size in bytes
256a3667aaeSNaresh Kumar Inna */
257a3667aaeSNaresh Kumar Inna uint32_t sf_nsec; /* # of flash sectors */
258a3667aaeSNaresh Kumar Inna struct pci_params pci;
259a3667aaeSNaresh Kumar Inna uint32_t log_level; /* Module-level for
260a3667aaeSNaresh Kumar Inna * debug log.
261a3667aaeSNaresh Kumar Inna */
262a3667aaeSNaresh Kumar Inna };
263a3667aaeSNaresh Kumar Inna
264a3667aaeSNaresh Kumar Inna struct csio_vpd {
265a3667aaeSNaresh Kumar Inna uint32_t cclk;
266a3667aaeSNaresh Kumar Inna uint8_t ec[EC_LEN + 1];
267a3667aaeSNaresh Kumar Inna uint8_t sn[SERNUM_LEN + 1];
268a3667aaeSNaresh Kumar Inna uint8_t id[ID_LEN + 1];
269a3667aaeSNaresh Kumar Inna };
270a3667aaeSNaresh Kumar Inna
271e1735d9aSVarun Prakash /* Firmware Port Capabilities types. */
272e1735d9aSVarun Prakash
273e1735d9aSVarun Prakash typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
274e1735d9aSVarun Prakash typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
275e1735d9aSVarun Prakash
276e1735d9aSVarun Prakash enum fw_caps {
277e1735d9aSVarun Prakash FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
278e1735d9aSVarun Prakash FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
279e1735d9aSVarun Prakash FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
280e1735d9aSVarun Prakash };
281e1735d9aSVarun Prakash
282e1735d9aSVarun Prakash enum cc_pause {
283e1735d9aSVarun Prakash PAUSE_RX = 1 << 0,
284e1735d9aSVarun Prakash PAUSE_TX = 1 << 1,
285e1735d9aSVarun Prakash PAUSE_AUTONEG = 1 << 2
286e1735d9aSVarun Prakash };
287e1735d9aSVarun Prakash
288e1735d9aSVarun Prakash enum cc_fec {
289e1735d9aSVarun Prakash FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
290e1735d9aSVarun Prakash FEC_RS = 1 << 1, /* Reed-Solomon */
291e1735d9aSVarun Prakash FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
292e1735d9aSVarun Prakash };
293e1735d9aSVarun Prakash
294e1735d9aSVarun Prakash struct link_config {
295e1735d9aSVarun Prakash fw_port_cap32_t pcaps; /* link capabilities */
296e1735d9aSVarun Prakash fw_port_cap32_t def_acaps; /* default advertised capabilities */
297e1735d9aSVarun Prakash fw_port_cap32_t acaps; /* advertised capabilities */
298e1735d9aSVarun Prakash fw_port_cap32_t lpacaps; /* peer advertised capabilities */
299e1735d9aSVarun Prakash
300e1735d9aSVarun Prakash fw_port_cap32_t speed_caps; /* speed(s) user has requested */
301e1735d9aSVarun Prakash unsigned int speed; /* actual link speed (Mb/s) */
302e1735d9aSVarun Prakash
303e1735d9aSVarun Prakash enum cc_pause requested_fc; /* flow control user has requested */
304e1735d9aSVarun Prakash enum cc_pause fc; /* actual link flow control */
305e1735d9aSVarun Prakash
306e1735d9aSVarun Prakash enum cc_fec requested_fec; /* Forward Error Correction: */
307e1735d9aSVarun Prakash enum cc_fec fec; /* requested and actual in use */
308e1735d9aSVarun Prakash
309e1735d9aSVarun Prakash unsigned char autoneg; /* autonegotiating? */
310e1735d9aSVarun Prakash
311e1735d9aSVarun Prakash unsigned char link_ok; /* link up? */
312e1735d9aSVarun Prakash unsigned char link_down_rc; /* link down reason */
313e1735d9aSVarun Prakash };
314e1735d9aSVarun Prakash
315e1735d9aSVarun Prakash #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
316e1735d9aSVarun Prakash
317e1735d9aSVarun Prakash #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
318e1735d9aSVarun Prakash FW_PORT_CAP32_ANEG)
319e1735d9aSVarun Prakash
320e1735d9aSVarun Prakash /* Enable or disable autonegotiation. */
321e1735d9aSVarun Prakash #define AUTONEG_DISABLE 0x00
322e1735d9aSVarun Prakash #define AUTONEG_ENABLE 0x01
323e1735d9aSVarun Prakash
324a3667aaeSNaresh Kumar Inna struct csio_pport {
325a3667aaeSNaresh Kumar Inna uint16_t pcap;
326e1735d9aSVarun Prakash uint16_t acap;
327a3667aaeSNaresh Kumar Inna uint8_t portid;
328a3667aaeSNaresh Kumar Inna uint8_t link_status;
329a3667aaeSNaresh Kumar Inna uint16_t link_speed;
330a3667aaeSNaresh Kumar Inna uint8_t mac[6];
331a3667aaeSNaresh Kumar Inna uint8_t mod_type;
332a3667aaeSNaresh Kumar Inna uint8_t rsvd1;
333a3667aaeSNaresh Kumar Inna uint8_t rsvd2;
334a3667aaeSNaresh Kumar Inna uint8_t rsvd3;
335e1735d9aSVarun Prakash struct link_config link_cfg;
336a3667aaeSNaresh Kumar Inna };
337a3667aaeSNaresh Kumar Inna
338a3667aaeSNaresh Kumar Inna /* fcoe resource information */
339a3667aaeSNaresh Kumar Inna struct csio_fcoe_res_info {
340a3667aaeSNaresh Kumar Inna uint16_t e_d_tov;
341a3667aaeSNaresh Kumar Inna uint16_t r_a_tov_seq;
342a3667aaeSNaresh Kumar Inna uint16_t r_a_tov_els;
343a3667aaeSNaresh Kumar Inna uint16_t r_r_tov;
344a3667aaeSNaresh Kumar Inna uint32_t max_xchgs;
345a3667aaeSNaresh Kumar Inna uint32_t max_ssns;
346a3667aaeSNaresh Kumar Inna uint32_t used_xchgs;
347a3667aaeSNaresh Kumar Inna uint32_t used_ssns;
348a3667aaeSNaresh Kumar Inna uint32_t max_fcfs;
349a3667aaeSNaresh Kumar Inna uint32_t max_vnps;
350a3667aaeSNaresh Kumar Inna uint32_t used_fcfs;
351a3667aaeSNaresh Kumar Inna uint32_t used_vnps;
352a3667aaeSNaresh Kumar Inna };
353a3667aaeSNaresh Kumar Inna
354a3667aaeSNaresh Kumar Inna /* HW State machine Events */
355a3667aaeSNaresh Kumar Inna enum csio_hw_ev {
356a3667aaeSNaresh Kumar Inna CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
357a3667aaeSNaresh Kumar Inna CSIO_HWE_INIT, /* Config done, start Init */
358a3667aaeSNaresh Kumar Inna CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
359a3667aaeSNaresh Kumar Inna CSIO_HWE_FATAL, /* Fatal error during initialization */
360a3667aaeSNaresh Kumar Inna CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
361a3667aaeSNaresh Kumar Inna CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
362a3667aaeSNaresh Kumar Inna CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
363a3667aaeSNaresh Kumar Inna CSIO_HWE_QUIESCED, /* HBA quiesced */
364a3667aaeSNaresh Kumar Inna CSIO_HWE_HBA_RESET, /* HBA reset requested */
365a3667aaeSNaresh Kumar Inna CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
366a3667aaeSNaresh Kumar Inna CSIO_HWE_FW_DLOAD, /* FW download requested */
367a3667aaeSNaresh Kumar Inna CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
368a3667aaeSNaresh Kumar Inna CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
369a3667aaeSNaresh Kumar Inna CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
370a3667aaeSNaresh Kumar Inna CSIO_HWE_MAX, /* Max HW event */
371a3667aaeSNaresh Kumar Inna };
372a3667aaeSNaresh Kumar Inna
373a3667aaeSNaresh Kumar Inna /* hw stats */
374a3667aaeSNaresh Kumar Inna struct csio_hw_stats {
375a3667aaeSNaresh Kumar Inna uint32_t n_evt_activeq; /* Number of event in active Q */
376a3667aaeSNaresh Kumar Inna uint32_t n_evt_freeq; /* Number of event in free Q */
377a3667aaeSNaresh Kumar Inna uint32_t n_evt_drop; /* Number of event droped */
378a3667aaeSNaresh Kumar Inna uint32_t n_evt_unexp; /* Number of unexpected events */
379a3667aaeSNaresh Kumar Inna uint32_t n_pcich_offline;/* Number of pci channel offline */
380a3667aaeSNaresh Kumar Inna uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
381a3667aaeSNaresh Kumar Inna uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
382a3667aaeSNaresh Kumar Inna uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
383a3667aaeSNaresh Kumar Inna uint32_t n_cpl_unexp; /* Number of unexpected cpl */
384a3667aaeSNaresh Kumar Inna uint32_t n_mbint_unexp; /* Number of unexpected mbox */
385a3667aaeSNaresh Kumar Inna /* interrupt */
386a3667aaeSNaresh Kumar Inna uint32_t n_plint_unexp; /* Number of unexpected PL */
387a3667aaeSNaresh Kumar Inna /* interrupt */
388a3667aaeSNaresh Kumar Inna uint32_t n_plint_cnt; /* Number of PL interrupt */
389a3667aaeSNaresh Kumar Inna uint32_t n_int_stray; /* Number of stray interrupt */
390a3667aaeSNaresh Kumar Inna uint32_t n_err; /* Number of hw errors */
391a3667aaeSNaresh Kumar Inna uint32_t n_err_fatal; /* Number of fatal errors */
392a3667aaeSNaresh Kumar Inna uint32_t n_err_nomem; /* Number of memory alloc failure */
393a3667aaeSNaresh Kumar Inna uint32_t n_err_io; /* Number of IO failure */
394a3667aaeSNaresh Kumar Inna enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
395a3667aaeSNaresh Kumar Inna uint64_t n_reset_start; /* Start time after the reset */
396a3667aaeSNaresh Kumar Inna uint32_t rsvd1;
397a3667aaeSNaresh Kumar Inna };
398a3667aaeSNaresh Kumar Inna
399a3667aaeSNaresh Kumar Inna /* Defines for hw->flags */
400a3667aaeSNaresh Kumar Inna #define CSIO_HWF_MASTER 0x00000001 /* This is the Master
401a3667aaeSNaresh Kumar Inna * function for the
402a3667aaeSNaresh Kumar Inna * card.
403a3667aaeSNaresh Kumar Inna */
404a3667aaeSNaresh Kumar Inna #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
405a3667aaeSNaresh Kumar Inna * enable bit set?
406a3667aaeSNaresh Kumar Inna */
407a3667aaeSNaresh Kumar Inna #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
408a3667aaeSNaresh Kumar Inna #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
409a3667aaeSNaresh Kumar Inna * allocated memory.
410a3667aaeSNaresh Kumar Inna */
411a3667aaeSNaresh Kumar Inna #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
412a3667aaeSNaresh Kumar Inna * allocated in FW.
413a3667aaeSNaresh Kumar Inna */
414a3667aaeSNaresh Kumar Inna #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
415a3667aaeSNaresh Kumar Inna #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
416a3667aaeSNaresh Kumar Inna * id cached */
417a3667aaeSNaresh Kumar Inna #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
418a3667aaeSNaresh Kumar Inna * FW events
419a3667aaeSNaresh Kumar Inna */
420a3667aaeSNaresh Kumar Inna #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
421a3667aaeSNaresh Kumar Inna * params
422a3667aaeSNaresh Kumar Inna */
423a3667aaeSNaresh Kumar Inna #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
424a3667aaeSNaresh Kumar Inna * enabled?
425a3667aaeSNaresh Kumar Inna */
426ff6e88f1SVarun Prakash #define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400 /* Is PCIe relaxed
427ff6e88f1SVarun Prakash * ordering enabled
428ff6e88f1SVarun Prakash */
429a3667aaeSNaresh Kumar Inna
430a3667aaeSNaresh Kumar Inna #define csio_is_hw_intr_enabled(__hw) \
431a3667aaeSNaresh Kumar Inna ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
432a3667aaeSNaresh Kumar Inna #define csio_is_host_intr_enabled(__hw) \
433a3667aaeSNaresh Kumar Inna ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
434a3667aaeSNaresh Kumar Inna #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
435a3667aaeSNaresh Kumar Inna #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
436a3667aaeSNaresh Kumar Inna #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
437a3667aaeSNaresh Kumar Inna #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
438a3667aaeSNaresh Kumar Inna #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
439a3667aaeSNaresh Kumar Inna
440a3667aaeSNaresh Kumar Inna /* Defines for intr_mode */
441a3667aaeSNaresh Kumar Inna enum csio_intr_mode {
442a3667aaeSNaresh Kumar Inna CSIO_IM_NONE = 0,
443a3667aaeSNaresh Kumar Inna CSIO_IM_INTX = 1,
444a3667aaeSNaresh Kumar Inna CSIO_IM_MSI = 2,
445a3667aaeSNaresh Kumar Inna CSIO_IM_MSIX = 3,
446a3667aaeSNaresh Kumar Inna };
447a3667aaeSNaresh Kumar Inna
448a3667aaeSNaresh Kumar Inna /* Master HW structure: One per function */
449a3667aaeSNaresh Kumar Inna struct csio_hw {
450a3667aaeSNaresh Kumar Inna struct csio_sm sm; /* State machine: should
451a3667aaeSNaresh Kumar Inna * be the 1st member.
452a3667aaeSNaresh Kumar Inna */
453a3667aaeSNaresh Kumar Inna spinlock_t lock; /* Lock for hw */
454a3667aaeSNaresh Kumar Inna
455a3667aaeSNaresh Kumar Inna struct csio_scsim scsim; /* SCSI module*/
456a3667aaeSNaresh Kumar Inna struct csio_wrm wrm; /* Work request module*/
457a3667aaeSNaresh Kumar Inna struct pci_dev *pdev; /* PCI device */
458a3667aaeSNaresh Kumar Inna
459a3667aaeSNaresh Kumar Inna void __iomem *regstart; /* Virtual address of
460a3667aaeSNaresh Kumar Inna * register map
461a3667aaeSNaresh Kumar Inna */
462a3667aaeSNaresh Kumar Inna /* SCSI queue sets */
463a3667aaeSNaresh Kumar Inna uint32_t num_sqsets; /* Number of SCSI
464a3667aaeSNaresh Kumar Inna * queue sets */
465a3667aaeSNaresh Kumar Inna uint32_t num_scsi_msix_cpus; /* Number of CPUs that
466a3667aaeSNaresh Kumar Inna * will be used
467a3667aaeSNaresh Kumar Inna * for ingress
468a3667aaeSNaresh Kumar Inna * processing.
469a3667aaeSNaresh Kumar Inna */
470a3667aaeSNaresh Kumar Inna
471a3667aaeSNaresh Kumar Inna struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
472a3667aaeSNaresh Kumar Inna struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
473a3667aaeSNaresh Kumar Inna
474a3667aaeSNaresh Kumar Inna uint32_t evtflag; /* Event flag */
475a3667aaeSNaresh Kumar Inna uint32_t flags; /* HW flags */
476a3667aaeSNaresh Kumar Inna
477a3667aaeSNaresh Kumar Inna struct csio_mgmtm mgmtm; /* management module */
478a3667aaeSNaresh Kumar Inna struct csio_mbm mbm; /* Mailbox module */
479a3667aaeSNaresh Kumar Inna
480a3667aaeSNaresh Kumar Inna /* Lnodes */
481a3667aaeSNaresh Kumar Inna uint32_t num_lns; /* Number of lnodes */
482a3667aaeSNaresh Kumar Inna struct csio_lnode *rln; /* Root lnode */
483a3667aaeSNaresh Kumar Inna struct list_head sln_head; /* Sibling node list
484a3667aaeSNaresh Kumar Inna * list
485a3667aaeSNaresh Kumar Inna */
486a3667aaeSNaresh Kumar Inna int intr_iq_idx; /* Forward interrupt
487a3667aaeSNaresh Kumar Inna * queue.
488a3667aaeSNaresh Kumar Inna */
489a3667aaeSNaresh Kumar Inna int fwevt_iq_idx; /* FW evt queue */
490a3667aaeSNaresh Kumar Inna struct work_struct evtq_work; /* Worker thread for
491a3667aaeSNaresh Kumar Inna * HW events.
492a3667aaeSNaresh Kumar Inna */
493a3667aaeSNaresh Kumar Inna struct list_head evt_free_q; /* freelist of evt
494a3667aaeSNaresh Kumar Inna * elements
495a3667aaeSNaresh Kumar Inna */
496a3667aaeSNaresh Kumar Inna struct list_head evt_active_q; /* active evt queue*/
497a3667aaeSNaresh Kumar Inna
498a3667aaeSNaresh Kumar Inna /* board related info */
499a3667aaeSNaresh Kumar Inna char name[32];
500a3667aaeSNaresh Kumar Inna char hw_ver[16];
501a3667aaeSNaresh Kumar Inna char model_desc[32];
502a3667aaeSNaresh Kumar Inna char drv_version[32];
503a3667aaeSNaresh Kumar Inna char fwrev_str[32];
504a3667aaeSNaresh Kumar Inna uint32_t optrom_ver;
505a3667aaeSNaresh Kumar Inna uint32_t fwrev;
506a3667aaeSNaresh Kumar Inna uint32_t tp_vers;
507a3667aaeSNaresh Kumar Inna char chip_ver;
5087cc16380SArvind Bhushan uint16_t chip_id; /* Tells T4/T5 chip */
509a3667aaeSNaresh Kumar Inna enum csio_dev_state fw_state;
510a3667aaeSNaresh Kumar Inna struct csio_vpd vpd;
511a3667aaeSNaresh Kumar Inna
512a3667aaeSNaresh Kumar Inna uint8_t pfn; /* Physical Function
513a3667aaeSNaresh Kumar Inna * number
514a3667aaeSNaresh Kumar Inna */
515a3667aaeSNaresh Kumar Inna uint32_t port_vec; /* Port vector */
516a3667aaeSNaresh Kumar Inna uint8_t num_pports; /* Number of physical
517a3667aaeSNaresh Kumar Inna * ports.
518a3667aaeSNaresh Kumar Inna */
519a3667aaeSNaresh Kumar Inna uint8_t rst_retries; /* Reset retries */
520a3667aaeSNaresh Kumar Inna uint8_t cur_evt; /* current s/m evt */
521a3667aaeSNaresh Kumar Inna uint8_t prev_evt; /* Previous s/m evt */
522a3667aaeSNaresh Kumar Inna uint32_t dev_num; /* device number */
523a3667aaeSNaresh Kumar Inna struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
524a3667aaeSNaresh Kumar Inna struct csio_hw_params params; /* Hw parameters */
525a3667aaeSNaresh Kumar Inna
526decab9a6SRomain Perier struct dma_pool *scsi_dma_pool; /* DMA pool for SCSI */
527a3667aaeSNaresh Kumar Inna mempool_t *mb_mempool; /* Mailbox memory pool*/
528a3667aaeSNaresh Kumar Inna mempool_t *rnode_mempool; /* rnode memory pool */
529a3667aaeSNaresh Kumar Inna
530a3667aaeSNaresh Kumar Inna /* Interrupt */
531a3667aaeSNaresh Kumar Inna enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
532a3667aaeSNaresh Kumar Inna uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
533a3667aaeSNaresh Kumar Inna * index
534a3667aaeSNaresh Kumar Inna */
535a3667aaeSNaresh Kumar Inna uint32_t nondata_intr_idx; /* nondata MSIX/intr
536a3667aaeSNaresh Kumar Inna * idx
537a3667aaeSNaresh Kumar Inna */
538a3667aaeSNaresh Kumar Inna
539a3667aaeSNaresh Kumar Inna uint8_t cfg_neq; /* FW configured no of
540a3667aaeSNaresh Kumar Inna * egress queues
541a3667aaeSNaresh Kumar Inna */
542a3667aaeSNaresh Kumar Inna uint8_t cfg_niq; /* FW configured no of
543a3667aaeSNaresh Kumar Inna * iq queues.
544a3667aaeSNaresh Kumar Inna */
545a3667aaeSNaresh Kumar Inna
546a3667aaeSNaresh Kumar Inna struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
5477cc16380SArvind Bhushan struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
5487cc16380SArvind Bhushan * Operations
5497cc16380SArvind Bhushan */
550a3667aaeSNaresh Kumar Inna
551a3667aaeSNaresh Kumar Inna /* MSIX vectors */
552a3667aaeSNaresh Kumar Inna struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
553a3667aaeSNaresh Kumar Inna
554a3667aaeSNaresh Kumar Inna struct dentry *debugfs_root; /* Debug FS */
555a3667aaeSNaresh Kumar Inna struct csio_hw_stats stats; /* Hw statistics */
556a3667aaeSNaresh Kumar Inna };
557a3667aaeSNaresh Kumar Inna
558a3667aaeSNaresh Kumar Inna /* Register access macros */
559a3667aaeSNaresh Kumar Inna #define csio_reg(_b, _r) ((_b) + (_r))
560a3667aaeSNaresh Kumar Inna
561a3667aaeSNaresh Kumar Inna #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
562a3667aaeSNaresh Kumar Inna #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
563a3667aaeSNaresh Kumar Inna #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
564a3667aaeSNaresh Kumar Inna #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
565a3667aaeSNaresh Kumar Inna
566a3667aaeSNaresh Kumar Inna #define csio_wr_reg8(_h, _v, _r) writeb((_v), \
567a3667aaeSNaresh Kumar Inna csio_reg((_h)->regstart, (_r)))
568a3667aaeSNaresh Kumar Inna #define csio_wr_reg16(_h, _v, _r) writew((_v), \
569a3667aaeSNaresh Kumar Inna csio_reg((_h)->regstart, (_r)))
570a3667aaeSNaresh Kumar Inna #define csio_wr_reg32(_h, _v, _r) writel((_v), \
571a3667aaeSNaresh Kumar Inna csio_reg((_h)->regstart, (_r)))
572a3667aaeSNaresh Kumar Inna #define csio_wr_reg64(_h, _v, _r) writeq((_v), \
573a3667aaeSNaresh Kumar Inna csio_reg((_h)->regstart, (_r)))
574a3667aaeSNaresh Kumar Inna
575a3667aaeSNaresh Kumar Inna void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
576a3667aaeSNaresh Kumar Inna
577a3667aaeSNaresh Kumar Inna /* Core clocks <==> uSecs */
578a3667aaeSNaresh Kumar Inna static inline uint32_t
csio_core_ticks_to_us(struct csio_hw * hw,uint32_t ticks)579a3667aaeSNaresh Kumar Inna csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
580a3667aaeSNaresh Kumar Inna {
581a3667aaeSNaresh Kumar Inna /* add Core Clock / 2 to round ticks to nearest uS */
582a3667aaeSNaresh Kumar Inna return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
583a3667aaeSNaresh Kumar Inna }
584a3667aaeSNaresh Kumar Inna
585a3667aaeSNaresh Kumar Inna static inline uint32_t
csio_us_to_core_ticks(struct csio_hw * hw,uint32_t us)586a3667aaeSNaresh Kumar Inna csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
587a3667aaeSNaresh Kumar Inna {
588a3667aaeSNaresh Kumar Inna return (us * hw->vpd.cclk) / 1000;
589a3667aaeSNaresh Kumar Inna }
590a3667aaeSNaresh Kumar Inna
591a3667aaeSNaresh Kumar Inna /* Easy access macros */
592a3667aaeSNaresh Kumar Inna #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
593a3667aaeSNaresh Kumar Inna #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
594a3667aaeSNaresh Kumar Inna #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
595a3667aaeSNaresh Kumar Inna #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
596a3667aaeSNaresh Kumar Inna
597a3667aaeSNaresh Kumar Inna #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
598a3667aaeSNaresh Kumar Inna #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
599a3667aaeSNaresh Kumar Inna #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
600a3667aaeSNaresh Kumar Inna
601a3667aaeSNaresh Kumar Inna #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
602a3667aaeSNaresh Kumar Inna #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
603a3667aaeSNaresh Kumar Inna #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
604a3667aaeSNaresh Kumar Inna #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
605a3667aaeSNaresh Kumar Inna
606a3667aaeSNaresh Kumar Inna /* Printing/logging */
607a3667aaeSNaresh Kumar Inna #define CSIO_DEVID(__dev) ((__dev)->dev_num)
608a3667aaeSNaresh Kumar Inna #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
609a3667aaeSNaresh Kumar Inna #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
610a3667aaeSNaresh Kumar Inna
611a3667aaeSNaresh Kumar Inna #define csio_info(__hw, __fmt, ...) \
612a3667aaeSNaresh Kumar Inna dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
613a3667aaeSNaresh Kumar Inna
614a3667aaeSNaresh Kumar Inna #define csio_fatal(__hw, __fmt, ...) \
615a3667aaeSNaresh Kumar Inna dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
616a3667aaeSNaresh Kumar Inna
617a3667aaeSNaresh Kumar Inna #define csio_err(__hw, __fmt, ...) \
618a3667aaeSNaresh Kumar Inna dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
619a3667aaeSNaresh Kumar Inna
620a3667aaeSNaresh Kumar Inna #define csio_warn(__hw, __fmt, ...) \
621a3667aaeSNaresh Kumar Inna dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
622a3667aaeSNaresh Kumar Inna
623a3667aaeSNaresh Kumar Inna #ifdef __CSIO_DEBUG__
624a3667aaeSNaresh Kumar Inna #define csio_dbg(__hw, __fmt, ...) \
625a3667aaeSNaresh Kumar Inna csio_info((__hw), __fmt, ##__VA_ARGS__);
626a3667aaeSNaresh Kumar Inna #else
627a3667aaeSNaresh Kumar Inna #define csio_dbg(__hw, __fmt, ...)
628a3667aaeSNaresh Kumar Inna #endif
629a3667aaeSNaresh Kumar Inna
6307cc16380SArvind Bhushan int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
6317cc16380SArvind Bhushan int, int, uint32_t *);
6327cc16380SArvind Bhushan void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
6337cc16380SArvind Bhushan unsigned int, unsigned int);
634a3667aaeSNaresh Kumar Inna int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
635a3667aaeSNaresh Kumar Inna void csio_hw_intr_disable(struct csio_hw *);
6367cc16380SArvind Bhushan int csio_hw_slow_intr_handler(struct csio_hw *);
6377cc16380SArvind Bhushan int csio_handle_intr_status(struct csio_hw *, unsigned int,
6387cc16380SArvind Bhushan const struct intr_info *);
6397cc16380SArvind Bhushan
640e1735d9aSVarun Prakash fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps);
641e1735d9aSVarun Prakash fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
642*68bdc630SVarun Prakash fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32);
643e1735d9aSVarun Prakash fw_port_cap32_t lstatus_to_fwcap(u32 lstatus);
644e1735d9aSVarun Prakash
645a3667aaeSNaresh Kumar Inna int csio_hw_start(struct csio_hw *);
646a3667aaeSNaresh Kumar Inna int csio_hw_stop(struct csio_hw *);
647a3667aaeSNaresh Kumar Inna int csio_hw_reset(struct csio_hw *);
648a3667aaeSNaresh Kumar Inna int csio_is_hw_ready(struct csio_hw *);
649a3667aaeSNaresh Kumar Inna int csio_is_hw_removing(struct csio_hw *);
650a3667aaeSNaresh Kumar Inna
651a3667aaeSNaresh Kumar Inna int csio_fwevtq_handler(struct csio_hw *);
652a3667aaeSNaresh Kumar Inna void csio_evtq_worker(struct work_struct *);
6537cc16380SArvind Bhushan int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
654a3667aaeSNaresh Kumar Inna void csio_evtq_flush(struct csio_hw *hw);
655a3667aaeSNaresh Kumar Inna
656a3667aaeSNaresh Kumar Inna int csio_request_irqs(struct csio_hw *);
657a3667aaeSNaresh Kumar Inna void csio_intr_enable(struct csio_hw *);
658a3667aaeSNaresh Kumar Inna void csio_intr_disable(struct csio_hw *, bool);
6597cc16380SArvind Bhushan void csio_hw_fatal_err(struct csio_hw *);
660a3667aaeSNaresh Kumar Inna
661a3667aaeSNaresh Kumar Inna struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
662a3667aaeSNaresh Kumar Inna int csio_config_queues(struct csio_hw *);
663a3667aaeSNaresh Kumar Inna
664a3667aaeSNaresh Kumar Inna int csio_hw_init(struct csio_hw *);
665a3667aaeSNaresh Kumar Inna void csio_hw_exit(struct csio_hw *);
666a3667aaeSNaresh Kumar Inna #endif /* ifndef __CSIO_HW_H__ */
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