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/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CCI Cache Coherent Interconnect
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
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/linux/drivers/bus/
H A Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
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/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
45 tristate "Arm CMN-600 PMU support"
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 cpu-map {
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
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H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
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/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
14 #include <linux/arm-cci.h>
19 #include <linux/irqchip/arm-gic.h>
70 /* R_CPUCFG registers, specific to sun8i-a83t */
110 is_compatible = of_device_is_compatible(node, "arm,cortex-a15"); in sunxi_core_is_cortex_a15()
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/linux/drivers/usb/typec/ucsi/
H A Ducsi_ccg.c1 // SPDX-License-Identifier: GPL-2.0
3 * UCSI driver for Cypress CCGx Type-C controller
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
26 FW1, /* FW partition-1 (contains secondary fw) */
27 FW2, /* FW partition-2 (contains primary fw) */
197 __le32 cci; member
231 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
240 struct i2c_client *client = uc->client; in ccg_read()
241 const struct i2c_adapter_quirks *quirks = client->adapter->quirks; in ccg_read()
245 .addr = client->addr, in ccg_read()
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <2>;
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/linux/drivers/pmdomain/amlogic/
H A Dmeson-secure-pwrc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 #include <dt-bindings/power/meson-a1-power.h>
14 #include <dt-bindings/power/amlogic,c3-pwrc.h>
15 #include <dt-bindings/power/meson-s4-power.h>
16 #include <dt-bindings/power/amlogic,t7-pwrc.h>
17 #include <dt-bindings/power/amlogic,a4-pwrc.h>
18 #include <dt-bindings/power/amlogic,a5-pwrc.h>
19 #include <linux/arm-smccc.h>
57 if (meson_sm_call(pwrc_domain->pwrc->fw, SM_A1_PWRC_GET, &is_off, in pwrc_secure_is_off()
58 pwrc_domain->index, 0, 0, 0, 0) < 0) in pwrc_secure_is_off()
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
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/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/exynos7885.h>
17 #include "clk-exynos-arm64.h"
25 /* ---- CMU_TOP ------------------------------------------------------------- */
363 CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
366 /* ---- CMU_PERI ------------------------------------------------------------ */
583 CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
586 /* ---- CMU_CORE ------------------------------------------------------------ */
644 /* CCI (interconnect) clock must be always running */
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/linux/drivers/power/supply/
H A Dcpcap-battery.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Copyright (C) 2009-2010 Motorola, Inc.
23 #include <linux/nvmem-consumer.h>
28 #include <linux/mfd/motorola-cpcap.h>
32 * map to MC13783UG.pdf "Table 5-19. Register 13, Power Control 0"
141 #define CPCAP_NO_BATTERY -400
153 return &ddata->state[state]; in cpcap_battery_get_state()
186 channel = ddata->channels[CPCAP_BATTERY_IIO_BATTDET]; in cpcap_charger_battery_temperature()
190 dev_warn(ddata->dev, "%s failed: %i\n", __func__, error); in cpcap_charger_battery_temperature()
206 channel = ddata->channels[CPCAP_BATTERY_IIO_VOLTAGE]; in cpcap_battery_get_voltage()
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