Lines Matching +full:cci +full:- +full:400
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <2>;
26 #size-cells = <2>;
29 u-boot {
30 compatible = "u-boot,config";
31 bootscr-address = /bits/ 64 <0x20000000>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 #cooling-cells = <2>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 operating-points-v2 = <&cpu_opp_table>;
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 next-level-cache = <&L2>;
51 #cooling-cells = <2>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
58 next-level-cache = <&L2>;
62 #cooling-cells = <2>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
67 operating-points-v2 = <&cpu_opp_table>;
68 cpu-idle-states = <&CPU_SLEEP_0>;
69 next-level-cache = <&L2>;
73 #cooling-cells = <2>;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
78 operating-points-v2 = <&cpu_opp_table>;
79 cpu-idle-states = <&CPU_SLEEP_0>;
80 next-level-cache = <&L2>;
83 L2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP_0: cpu-sleep-0 {
93 compatible = "arm,idle-state";
94 arm,psci-suspend-param = <0x40000000>;
95 local-timer-stop;
96 entry-latency-us = <300>;
97 exit-latency-us = <600>;
98 min-residency-us = <10000>;
103 cpu_opp_table: opp-table-cpu {
104 compatible = "operating-points-v2";
105 opp-shared;
107 opp-hz = /bits/ 64 <1199999988>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <500000>;
112 opp-hz = /bits/ 64 <599999994>;
113 opp-microvolt = <1000000>;
114 clock-latency-ns = <500000>;
117 opp-hz = /bits/ 64 <399999996>;
118 opp-microvolt = <1000000>;
119 clock-latency-ns = <500000>;
122 opp-hz = /bits/ 64 <299999997>;
123 opp-microvolt = <1000000>;
124 clock-latency-ns = <500000>;
128 reserved-memory {
129 #address-cells = <2>;
130 #size-cells = <2>;
134 no-map;
139 no-map;
144 zynqmp_ipi: zynqmp-ipi {
145 bootph-all;
146 compatible = "xlnx,zynqmp-ipi-mailbox";
147 interrupt-parent = <&gic>;
149 xlnx,ipi-id = <0>;
150 #address-cells = <2>;
151 #size-cells = <2>;
155 bootph-all;
156 compatible = "xlnx,zynqmp-ipi-dest-mailbox";
161 reg-names = "local_request_region",
165 #mbox-cells = <1>;
166 xlnx,ipi-id = <4>;
173 bootph-all;
177 compatible = "arm,cortex-a53-pmu";
178 interrupt-parent = <&gic>;
183 interrupt-affinity = <&cpu0>,
190 compatible = "arm,psci-0.2";
196 compatible = "linaro,optee-tz";
200 zynqmp_firmware: zynqmp-firmware {
201 compatible = "xlnx,zynqmp-firmware";
202 #power-domain-cells = <1>;
204 bootph-all;
206 zynqmp_power: power-management {
207 bootph-all;
208 compatible = "xlnx,zynqmp-power";
209 interrupt-parent = <&gic>;
212 mbox-names = "tx", "rx";
215 soc-nvmem {
216 compatible = "xlnx,zynqmp-nvmem-fw";
217 nvmem-layout {
218 compatible = "fixed-layout";
219 #address-cells = <1>;
220 #size-cells = <1>;
222 soc_revision: soc-revision@0 {
226 efuse_dna: efuse-dna@c {
229 efuse_usr0: efuse-usr0@20 {
232 efuse_usr1: efuse-usr1@24 {
235 efuse_usr2: efuse-usr2@28 {
238 efuse_usr3: efuse-usr3@2c {
241 efuse_usr4: efuse-usr4@30 {
244 efuse_usr5: efuse-usr5@34 {
247 efuse_usr6: efuse-usr6@38 {
250 efuse_usr7: efuse-usr7@3c {
253 efuse_miscusr: efuse-miscusr@40 {
256 efuse_chash: efuse-chash@50 {
259 efuse_pufmisc: efuse-pufmisc@54 {
262 efuse_sec: efuse-sec@58 {
265 efuse_spkid: efuse-spkid@5c {
268 efuse_aeskey: efuse-aeskey@60 {
271 efuse_ppk0hash: efuse-ppk0hash@a0 {
274 efuse_ppk1hash: efuse-ppk1hash@d0 {
277 efuse_pufuser: efuse-pufuser@100 {
284 compatible = "xlnx,zynqmp-pcap-fpga";
287 xlnx_aes: zynqmp-aes {
288 compatible = "xlnx,zynqmp-aes";
291 zynqmp_reset: reset-controller {
292 compatible = "xlnx,zynqmp-reset";
293 #reset-cells = <1>;
297 compatible = "xlnx,zynqmp-pinctrl";
302 compatible = "xlnx,zynqmp-gpio-modepin";
303 gpio-controller;
304 #gpio-cells = <2>;
310 compatible = "arm,armv8-timer";
311 interrupt-parent = <&gic>;
318 fpga_full: fpga-region {
319 compatible = "fpga-region";
320 fpga-mgr = <&zynqmp_pcap>;
321 #address-cells = <2>;
322 #size-cells = <2>;
327 compatible = "xlnx,zynqmp-r5fss";
328 xlnx,cluster-mode = <1>;
329 xlnx,tcm-mode = <1>;
331 #address-cells = <2>;
332 #size-cells = <2>;
340 compatible = "xlnx,zynqmp-r5f";
345 reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
346 power-domains = <&zynqmp_firmware PD_RPU_0>,
351 memory-region = <&rproc_0_fw_image>;
355 compatible = "xlnx,zynqmp-r5f";
357 reg-names = "atcm0", "btcm0";
358 power-domains = <&zynqmp_firmware PD_RPU_1>,
361 memory-region = <&rproc_1_fw_image>;
365 rproc_split: remoteproc-split@ffe00000 {
367 compatible = "xlnx,zynqmp-r5fss";
368 xlnx,cluster-mode = <0>;
369 xlnx,tcm-mode = <0>;
371 #address-cells = <2>;
372 #size-cells = <2>;
380 compatible = "xlnx,zynqmp-r5f";
382 reg-names = "atcm0", "btcm0";
383 power-domains = <&zynqmp_firmware PD_RPU_0>,
386 memory-region = <&rproc_0_fw_image>;
390 compatible = "xlnx,zynqmp-r5f";
392 reg-names = "atcm0", "btcm0";
393 power-domains = <&zynqmp_firmware PD_RPU_1>,
396 memory-region = <&rproc_1_fw_image>;
401 compatible = "iio-hwmon";
402 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
415 tsens_apu: thermal-sensor-apu {
416 compatible = "generic-adc-thermal";
417 #thermal-sensor-cells = <0>;
418 io-channels = <&xilinx_ams 7>;
419 io-channel-names = "sensor-channel";
422 tsens_rpu: thermal-sensor-rpu {
423 compatible = "generic-adc-thermal";
424 #thermal-sensor-cells = <0>;
425 io-channels = <&xilinx_ams 8>;
426 io-channel-names = "sensor-channel";
429 tsens_pl: thermal-sensor-pl {
430 compatible = "generic-adc-thermal";
431 #thermal-sensor-cells = <0>;
432 io-channels = <&xilinx_ams 20>;
433 io-channel-names = "sensor-channel";
436 thermal-zones {
437 apu-thermal {
438 polling-delay-passive = <1000>;
439 polling-delay = <5000>;
440 thermal-sensors = <&tsens_apu>;
456 cooling-maps {
459 cooling-device =
468 rpu-thermal {
469 polling-delay = <10000>;
470 thermal-sensors = <&tsens_rpu>;
481 pl-thermal {
482 polling-delay = <10000>;
483 thermal-sensors = <&tsens_pl>;
496 compatible = "simple-bus";
497 bootph-all;
498 #address-cells = <2>;
499 #size-cells = <2>;
503 compatible = "xlnx,zynq-can-1.0";
505 clock-names = "can_clk", "pclk";
508 interrupt-parent = <&gic>;
509 tx-fifo-depth = <0x40>;
510 rx-fifo-depth = <0x40>;
512 power-domains = <&zynqmp_firmware PD_CAN_0>;
516 compatible = "xlnx,zynq-can-1.0";
518 clock-names = "can_clk", "pclk";
521 interrupt-parent = <&gic>;
522 tx-fifo-depth = <0x40>;
523 rx-fifo-depth = <0x40>;
525 power-domains = <&zynqmp_firmware PD_CAN_1>;
528 cci: cci@fd6e0000 { label
529 compatible = "arm,cci-400";
533 #address-cells = <1>;
534 #size-cells = <1>;
537 compatible = "arm,cci-400-pmu,r1";
539 interrupt-parent = <&gic>;
549 compatible = "arm,coresight-cpu-debug", "arm,primecell";
551 clock-names = "apb_pclk";
556 compatible = "arm,coresight-cpu-debug", "arm,primecell";
558 clock-names = "apb_pclk";
563 compatible = "arm,coresight-cpu-debug", "arm,primecell";
565 clock-names = "apb_pclk";
570 compatible = "arm,coresight-cpu-debug", "arm,primecell";
572 clock-names = "apb_pclk";
577 fpd_dma_chan1: dma-controller@fd500000 {
579 compatible = "xlnx,zynqmp-dma-1.0";
581 interrupt-parent = <&gic>;
583 clock-names = "clk_main", "clk_apb";
584 #dma-cells = <1>;
585 xlnx,bus-width = <128>;
587 power-domains = <&zynqmp_firmware PD_GDMA>;
590 fpd_dma_chan2: dma-controller@fd510000 {
592 compatible = "xlnx,zynqmp-dma-1.0";
594 interrupt-parent = <&gic>;
596 clock-names = "clk_main", "clk_apb";
597 #dma-cells = <1>;
598 xlnx,bus-width = <128>;
600 power-domains = <&zynqmp_firmware PD_GDMA>;
603 fpd_dma_chan3: dma-controller@fd520000 {
605 compatible = "xlnx,zynqmp-dma-1.0";
607 interrupt-parent = <&gic>;
609 clock-names = "clk_main", "clk_apb";
610 #dma-cells = <1>;
611 xlnx,bus-width = <128>;
613 power-domains = <&zynqmp_firmware PD_GDMA>;
616 fpd_dma_chan4: dma-controller@fd530000 {
618 compatible = "xlnx,zynqmp-dma-1.0";
620 interrupt-parent = <&gic>;
622 clock-names = "clk_main", "clk_apb";
623 #dma-cells = <1>;
624 xlnx,bus-width = <128>;
626 power-domains = <&zynqmp_firmware PD_GDMA>;
629 fpd_dma_chan5: dma-controller@fd540000 {
631 compatible = "xlnx,zynqmp-dma-1.0";
633 interrupt-parent = <&gic>;
635 clock-names = "clk_main", "clk_apb";
636 #dma-cells = <1>;
637 xlnx,bus-width = <128>;
639 power-domains = <&zynqmp_firmware PD_GDMA>;
642 fpd_dma_chan6: dma-controller@fd550000 {
644 compatible = "xlnx,zynqmp-dma-1.0";
646 interrupt-parent = <&gic>;
648 clock-names = "clk_main", "clk_apb";
649 #dma-cells = <1>;
650 xlnx,bus-width = <128>;
652 power-domains = <&zynqmp_firmware PD_GDMA>;
655 fpd_dma_chan7: dma-controller@fd560000 {
657 compatible = "xlnx,zynqmp-dma-1.0";
659 interrupt-parent = <&gic>;
661 clock-names = "clk_main", "clk_apb";
662 #dma-cells = <1>;
663 xlnx,bus-width = <128>;
665 power-domains = <&zynqmp_firmware PD_GDMA>;
668 fpd_dma_chan8: dma-controller@fd570000 {
670 compatible = "xlnx,zynqmp-dma-1.0";
672 interrupt-parent = <&gic>;
674 clock-names = "clk_main", "clk_apb";
675 #dma-cells = <1>;
676 xlnx,bus-width = <128>;
678 power-domains = <&zynqmp_firmware PD_GDMA>;
681 gic: interrupt-controller@f9010000 {
682 compatible = "arm,gic-400";
683 #interrupt-cells = <3>;
688 interrupt-controller;
689 interrupt-parent = <&gic>;
695 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
697 interrupt-parent = <&gic>;
704 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
705 clock-names = "bus", "core";
706 power-domains = <&zynqmp_firmware PD_GPU>;
713 lpd_dma_chan1: dma-controller@ffa80000 {
715 compatible = "xlnx,zynqmp-dma-1.0";
717 interrupt-parent = <&gic>;
719 clock-names = "clk_main", "clk_apb";
720 #dma-cells = <1>;
721 xlnx,bus-width = <64>;
723 power-domains = <&zynqmp_firmware PD_ADMA>;
726 lpd_dma_chan2: dma-controller@ffa90000 {
728 compatible = "xlnx,zynqmp-dma-1.0";
730 interrupt-parent = <&gic>;
732 clock-names = "clk_main", "clk_apb";
733 #dma-cells = <1>;
734 xlnx,bus-width = <64>;
736 power-domains = <&zynqmp_firmware PD_ADMA>;
739 lpd_dma_chan3: dma-controller@ffaa0000 {
741 compatible = "xlnx,zynqmp-dma-1.0";
743 interrupt-parent = <&gic>;
745 clock-names = "clk_main", "clk_apb";
746 #dma-cells = <1>;
747 xlnx,bus-width = <64>;
749 power-domains = <&zynqmp_firmware PD_ADMA>;
752 lpd_dma_chan4: dma-controller@ffab0000 {
754 compatible = "xlnx,zynqmp-dma-1.0";
756 interrupt-parent = <&gic>;
758 clock-names = "clk_main", "clk_apb";
759 #dma-cells = <1>;
760 xlnx,bus-width = <64>;
762 power-domains = <&zynqmp_firmware PD_ADMA>;
765 lpd_dma_chan5: dma-controller@ffac0000 {
767 compatible = "xlnx,zynqmp-dma-1.0";
769 interrupt-parent = <&gic>;
771 clock-names = "clk_main", "clk_apb";
772 #dma-cells = <1>;
773 xlnx,bus-width = <64>;
775 power-domains = <&zynqmp_firmware PD_ADMA>;
778 lpd_dma_chan6: dma-controller@ffad0000 {
780 compatible = "xlnx,zynqmp-dma-1.0";
782 interrupt-parent = <&gic>;
784 clock-names = "clk_main", "clk_apb";
785 #dma-cells = <1>;
786 xlnx,bus-width = <64>;
788 power-domains = <&zynqmp_firmware PD_ADMA>;
791 lpd_dma_chan7: dma-controller@ffae0000 {
793 compatible = "xlnx,zynqmp-dma-1.0";
795 interrupt-parent = <&gic>;
797 clock-names = "clk_main", "clk_apb";
798 #dma-cells = <1>;
799 xlnx,bus-width = <64>;
801 power-domains = <&zynqmp_firmware PD_ADMA>;
804 lpd_dma_chan8: dma-controller@ffaf0000 {
806 compatible = "xlnx,zynqmp-dma-1.0";
808 interrupt-parent = <&gic>;
810 clock-names = "clk_main", "clk_apb";
811 #dma-cells = <1>;
812 xlnx,bus-width = <64>;
814 power-domains = <&zynqmp_firmware PD_ADMA>;
817 mc: memory-controller@fd070000 {
818 compatible = "xlnx,zynqmp-ddrc-2.40a";
820 interrupt-parent = <&gic>;
824 nand0: nand-controller@ff100000 {
825 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
828 clock-names = "controller", "bus";
829 interrupt-parent = <&gic>;
831 #address-cells = <1>;
832 #size-cells = <0>;
834 power-domains = <&zynqmp_firmware PD_NAND>;
838 compatible = "xlnx,zynqmp-gem", "cdns,gem";
840 interrupt-parent = <&gic>;
844 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
846 power-domains = <&zynqmp_firmware PD_ETH_0>;
848 reset-names = "gem0_rst";
852 compatible = "xlnx,zynqmp-gem", "cdns,gem";
854 interrupt-parent = <&gic>;
858 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
860 power-domains = <&zynqmp_firmware PD_ETH_1>;
862 reset-names = "gem1_rst";
866 compatible = "xlnx,zynqmp-gem", "cdns,gem";
868 interrupt-parent = <&gic>;
872 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
874 power-domains = <&zynqmp_firmware PD_ETH_2>;
876 reset-names = "gem2_rst";
880 compatible = "xlnx,zynqmp-gem", "cdns,gem";
882 interrupt-parent = <&gic>;
886 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
888 power-domains = <&zynqmp_firmware PD_ETH_3>;
890 reset-names = "gem3_rst";
894 compatible = "xlnx,zynqmp-gpio-1.0";
896 #gpio-cells = <0x2>;
897 gpio-controller;
898 interrupt-parent = <&gic>;
900 interrupt-controller;
901 #interrupt-cells = <2>;
903 power-domains = <&zynqmp_firmware PD_GPIO>;
907 compatible = "cdns,i2c-r1p14";
909 interrupt-parent = <&gic>;
911 clock-frequency = <400000>;
913 #address-cells = <1>;
914 #size-cells = <0>;
915 power-domains = <&zynqmp_firmware PD_I2C_0>;
919 compatible = "cdns,i2c-r1p14";
921 interrupt-parent = <&gic>;
923 clock-frequency = <400000>;
925 #address-cells = <1>;
926 #size-cells = <0>;
927 power-domains = <&zynqmp_firmware PD_I2C_1>;
930 ocm: memory-controller@ff960000 {
931 compatible = "xlnx,zynqmp-ocmc-1.0";
933 interrupt-parent = <&gic>;
938 compatible = "xlnx,nwl-pcie-2.11";
940 #address-cells = <3>;
941 #size-cells = <2>;
942 #interrupt-cells = <1>;
943 msi-controller;
945 interrupt-parent = <&gic>;
951 interrupt-names = "misc", "dummy", "intx",
953 msi-parent = <&pcie>;
957 reg-names = "breg", "pcireg", "cfg";
958 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
960 bus-range = <0x00 0xff>;
961 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
962 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
967 power-domains = <&zynqmp_firmware PD_PCIE>;
968 pcie_intc: legacy-interrupt-controller {
969 interrupt-controller;
970 #address-cells = <0>;
971 #interrupt-cells = <1>;
976 bootph-all;
977 compatible = "xlnx,zynqmp-qspi-1.0";
979 clock-names = "ref_clk", "pclk";
981 interrupt-parent = <&gic>;
982 num-cs = <1>;
985 #address-cells = <1>;
986 #size-cells = <0>;
988 power-domains = <&zynqmp_firmware PD_QSPI>;
992 compatible = "xlnx,zynqmp-psgtr-v1.1";
996 reg-names = "serdes", "siou";
997 #phy-cells = <4>;
1001 compatible = "xlnx,zynqmp-rtc";
1004 interrupt-parent = <&gic>;
1007 interrupt-names = "alarm", "sec";
1012 compatible = "ceva,ahci-1v84";
1015 interrupt-parent = <&gic>;
1017 power-domains = <&zynqmp_firmware PD_SATA>;
1023 bootph-all;
1024 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
1026 interrupt-parent = <&gic>;
1029 clock-names = "clk_xin", "clk_ahb";
1031 #clock-cells = <1>;
1032 clock-output-names = "clk_out_sd0", "clk_in_sd0";
1033 power-domains = <&zynqmp_firmware PD_SD_0>;
1038 bootph-all;
1039 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
1041 interrupt-parent = <&gic>;
1044 clock-names = "clk_xin", "clk_ahb";
1046 #clock-cells = <1>;
1047 clock-output-names = "clk_out_sd1", "clk_in_sd1";
1048 power-domains = <&zynqmp_firmware PD_SD_1>;
1053 compatible = "arm,mmu-500";
1055 #iommu-cells = <1>;
1057 #global-interrupts = <1>;
1058 interrupt-parent = <&gic>;
1079 compatible = "cdns,spi-r1p6";
1081 interrupt-parent = <&gic>;
1084 clock-names = "ref_clk", "pclk";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 power-domains = <&zynqmp_firmware PD_SPI_0>;
1091 compatible = "cdns,spi-r1p6";
1093 interrupt-parent = <&gic>;
1096 clock-names = "ref_clk", "pclk";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 power-domains = <&zynqmp_firmware PD_SPI_1>;
1105 interrupt-parent = <&gic>;
1110 timer-width = <32>;
1111 power-domains = <&zynqmp_firmware PD_TTC_0>;
1117 interrupt-parent = <&gic>;
1122 timer-width = <32>;
1123 power-domains = <&zynqmp_firmware PD_TTC_1>;
1129 interrupt-parent = <&gic>;
1134 timer-width = <32>;
1135 power-domains = <&zynqmp_firmware PD_TTC_2>;
1141 interrupt-parent = <&gic>;
1146 timer-width = <32>;
1147 power-domains = <&zynqmp_firmware PD_TTC_3>;
1151 bootph-all;
1152 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1154 interrupt-parent = <&gic>;
1157 clock-names = "uart_clk", "pclk";
1158 power-domains = <&zynqmp_firmware PD_UART_0>;
1163 bootph-all;
1164 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
1166 interrupt-parent = <&gic>;
1169 clock-names = "uart_clk", "pclk";
1170 power-domains = <&zynqmp_firmware PD_UART_1>;
1175 #address-cells = <2>;
1176 #size-cells = <2>;
1178 compatible = "xlnx,zynqmp-dwc3";
1180 clock-names = "bus_clk", "ref_clk";
1181 power-domains = <&zynqmp_firmware PD_USB_0>;
1185 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1186 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
1193 interrupt-parent = <&gic>;
1194 interrupt-names = "host", "peripheral", "otg", "wakeup";
1199 clock-names = "ref";
1201 snps,quirk-frame-length-adjustment = <0x20>;
1202 snps,resume-hs-terminations;
1203 /* dma-coherent; */
1208 #address-cells = <2>;
1209 #size-cells = <2>;
1211 compatible = "xlnx,zynqmp-dwc3";
1213 clock-names = "bus_clk", "ref_clk";
1214 power-domains = <&zynqmp_firmware PD_USB_1>;
1218 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
1225 interrupt-parent = <&gic>;
1226 interrupt-names = "host", "peripheral", "otg", "wakeup";
1231 clock-names = "ref";
1233 snps,quirk-frame-length-adjustment = <0x20>;
1234 snps,resume-hs-terminations;
1235 /* dma-coherent; */
1240 compatible = "cdns,wdt-r1p2";
1242 interrupt-parent = <&gic>;
1245 timeout-sec = <60>;
1246 reset-on-timeout;
1250 compatible = "cdns,wdt-r1p2";
1252 interrupt-parent = <&gic>;
1255 timeout-sec = <10>;
1259 compatible = "xlnx,zynqmp-ams";
1260 interrupt-parent = <&gic>;
1263 #address-cells = <1>;
1264 #size-cells = <1>;
1265 #io-channel-cells = <1>;
1268 ams_ps: ams-ps@0 {
1269 compatible = "xlnx,zynqmp-ams-ps";
1274 ams_pl: ams-pl@400 {
1275 compatible = "xlnx,zynqmp-ams-pl";
1281 zynqmp_dpdma: dma-controller@fd4c0000 {
1282 compatible = "xlnx,zynqmp-dpdma";
1286 interrupt-parent = <&gic>;
1287 clock-names = "axi_clk";
1288 power-domains = <&zynqmp_firmware PD_DP>;
1290 #dma-cells = <1>;
1294 bootph-all;
1295 compatible = "xlnx,zynqmp-dpsub-1.7";
1301 reg-names = "dp", "blend", "av_buf", "aud";
1303 interrupt-parent = <&gic>;
1305 clock-names = "dp_apb_clk", "dp_aud_clk",
1307 power-domains = <&zynqmp_firmware PD_DP>;
1309 dma-names = "vid0", "vid1", "vid2", "gfx0",
1319 #address-cells = <1>;
1320 #size-cells = <0>;