| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | tlb.json | 8 … refill, then this event only counts once. This event counts for refills caused by preload instruc…
12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio…
20 …n": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …caused by a miss in the L2 TLB driven by a memory access. Note that partial translations that also…
32 …caused by a miss in the L2 TLB driven by a memory access. Partial translations that also cause a t…
36 …caused by memory read operations. If there are multiple misses in the TLB that are resolved by the…
40 …caused by data side memory write operations. If there are multiple misses in the TLB that are reso…
44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even…
48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This…
[all …]
|
| H A D | l1d_cache.json | 4 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or s…
8 …. Each access to a cache line is counted including the multiple accesses caused by single instruct…
24 … accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data …
28 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load inst…
32 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed store ins…
44 …ictions from the level 1 data cache caused by a new cache line allocation. This event does not cou…
52 …nts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Mai…
|
| H A D | exception.json | 20 …"PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instructi…
24 …"PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SE…
44 …"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instru…
48 …"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data A…
|
| H A D | l1i_cache.json | 4 …"PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a misse…
8 …s which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenan…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | tlb.json | 8 … refill, then this event only counts once. This event counts for refills caused by preload instruc…
12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio…
20 …n": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, …
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …caused by a miss in the L2 TLB driven by a memory access. Note that partial translations that also…
32 …caused by a miss in the L2 TLB driven by a memory access. Partial translations that also cause a t…
36 …caused by memory read operations. If there are multiple misses in the TLB that are resolved by the…
40 …caused by data side memory write operations. If there are multiple misses in the TLB that are reso…
44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even…
48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This…
[all …]
|
| H A D | l1d_cache.json | 4 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or s…
8 …. Each access to a cache line is counted including the multiple accesses caused by single instruct…
20 … accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data …
24 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load inst…
28 …"PublicDescription": "Counts level 1 data cache refills caused by speculatively executed store ins…
40 …ictions from the level 1 data cache caused by a new cache line allocation. This event does not cou…
48 …nts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Mai…
|
| H A D | exception.json | 20 …"PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instructi…
24 …"PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SE…
44 …"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instru…
48 …"PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data A…
|
| H A D | l1i_cache.json | 4 …"PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a misse…
8 …s which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenan…
|
| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | cache.json | 45 …"PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.",
48 … "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch."
51 …"PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.",
54 … "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch."
57 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by demand access.",
60 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
63 "PublicDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch.",
66 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by hardware prefetch."
81 "PublicDescription": "This event counts L2D_CACHE_REFILL caused by demand access.",
84 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by demand access."
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
35 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
108 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. …
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
35 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
108 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. …
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
35 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T…
44 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
53 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
62 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
108 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. …
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | virtual-memory.json | 26 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T…
35 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This im…
44 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This…
53 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This im…
90 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. …
99 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
108 …"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. Thi…
117 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
154 …"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This im…
163 …"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | virtual-memory.json | 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
90 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
99 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
108 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
117 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
154 "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
163 "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused b
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | virtual-memory.json | 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
90 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
99 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
108 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
117 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
154 "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
163 "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused b
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | pipeline.json | 3 "PublicDescription": "A linefill caused an instruction side stall",
6 "BriefDescription": "A linefill caused an instruction side stall"
9 "PublicDescription": "A translation table walk caused an instruction side stall",
12 "BriefDescription": "A translation table walk caused an instruction side stall"
|
| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | pmc.json | 15 "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."
40 "BriefDescription": "The event selected for PMC5 caused the event counter to overflow."
85 "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."
115 "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."
130 "BriefDescription": "The event selected for PMC6 caused the event counter to overflow."
155 "BriefDescription": "The event selected for PMC3 caused the event counter to overflow."
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | pipeline.json | 9 "PublicDescription": "A linefill caused an instruction side stall",
12 "BriefDescription": "A linefill caused an instruction side stall"
15 "PublicDescription": "A translation table walk caused an instruction side stall",
18 "BriefDescription": "A translation table walk caused an instruction side stall"
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | virtual-memory.json | 26 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
35 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
53 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
90 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
154 "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
163 "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
172 "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | pipeline.json | 45 …d there is an interlock on an address operand. This type of interlock is caused by a load/store in…
48 …d there is an interlock on an address operand. This type of interlock is caused by a load/store in…
51 … event counts every cycle where there is a stall or an interlock that is caused by a VPU instructi…
54 … event counts every cycle where there is a stall or an interlock that is caused by a VPU instructi…
69 … to a load that is waiting on data. The event counts for stalls that are caused by missing the cac…
72 … to a load that is waiting on data. The event counts for stalls that are caused by missing the cac…
|
| /linux/drivers/extcon/ |
| H A D | extcon-axp288.c | 117 "Last wake caused by user pressing the power button",
118 "Last wake caused by a charger insertion",
119 "Last wake caused by a battery insertion",
120 "Last wake caused by SOC initiated global reset",
121 "Last wake caused by cold reset",
122 "Last shutdown caused by PMIC UVLO threshold",
123 "Last shutdown caused by SOC initiated cold off",
124 "Last shutdown caused by user pressing the power button",
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | memory.json | 35 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
44 "PublicDescription": "Number of times HLE caused a fault.",
247 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
256 "PublicDescription": "Number of times a RTM caused a fault.",
305 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
331 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
335 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | core.json | 5 "BriefDescription": "Retired Lock instructions which caused a bus lock.",
56 …with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottl…
68 …"BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, …
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 83 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
93 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
113 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
133 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
222 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
232 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
252 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
272 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
370 "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
390 "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused b
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l1i_cache.json | 4 …"PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a misse…
8 …s which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenan…
|