Searched full:cacheability (Results 1 – 19 of 19) sorted by relevance
118 cacheability attributes but is connected to a non-coherent169 cacheability attributes but is connected to a non-coherent
112 and cacheability attributes but are connected to a non-coherent204 cacheability attributes but is connected to a non-coherent
12 * mappings with different cacheability attributes for the same
15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
16 /* Cacheability attributes of MSM IOMMU mappings */
21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
41 li r3,0x1200 /* enable i-fetch cacheability */
172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
3204 * remove the cacheability attributes as in its_cpu_init_lpis()3230 * cacheability attributes as well. in its_cpu_init_lpis()5302 * remove the cacheability attributes as in its_probe_one()
1154 # MIPS allows mixing "slightly different" Cacheability and Coherency
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the144 * Cacheability and coherency controlled by the kernel automatically
313 * we then fully enforce cacheability of RAM, no matter what the guest
2330 * set on M7 processor. Compute the value of cacheability in paging_init()
2925 Chapter 5: Memory Accesses and Cacheability
215 * the cacheability of the kernel bits.
2989 Chapter 5: Memory Accesses and Cacheability
3107 Capítulo 5: Memory Accesses and Cacheability