Searched full:cacheability (Results 1 – 21 of 21) sorted by relevance
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,gic-v5.yaml | 118 cacheability attributes but is connected to a non-coherent
169 cacheability attributes but is connected to a non-coherent
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| /linux/arch/x86/include/asm/ |
| H A D | agp.h | 12 * mappings with different cacheability attributes for the same
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| H A D | set_memory.h | 15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
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| /linux/drivers/iommu/ |
| H A D | msm_iommu.h | 16 /* Cacheability attributes of MSM IOMMU mappings */
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| /linux/arch/sparc/include/asm/ |
| H A D | swift.h | 21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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| /linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_ppc970.S | 41 li r3,0x1200 /* enable i-fetch cacheability */
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| /linux/include/linux/ |
| H A D | io-pgtable.h | 84 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
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| /linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /linux/drivers/gpu/drm/imagination/ |
| H A D | pvr_rogue_meta.h | 277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
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| /linux/arch/riscv/ |
| H A D | Kconfig | 608 that indicate the cacheability, idempotency, and ordering
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| /linux/drivers/irqchip/ |
| H A D | irq-gic-v3-its.c | 3204 * remove the cacheability attributes as in its_cpu_init_lpis()
3230 * cacheability attributes as well. in its_cpu_init_lpis()
5306 * remove the cacheability attributes as in its_probe_one()
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| /linux/arch/mips/ |
| H A D | Kconfig | 1154 # MIPS allows mixing "slightly different" Cacheability and Coherency
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| /linux/include/uapi/drm/ |
| H A D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /linux/tools/include/uapi/drm/ |
| H A D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /linux/arch/arm64/kvm/ |
| H A D | mmu.c | 313 * we then fully enforce cacheability of RAM, no matter what the guest
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| /linux/arch/sparc/mm/ |
| H A D | init_64.c | 2330 * set on M7 processor. Compute the value of cacheability in paging_init()
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| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 2047 * Program cacheability overrides to not allocate cache in a6xx_llc_activate()
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| /linux/Documentation/translations/ko_KR/ |
| H A D | memory-barriers.txt | 2925 Chapter 5: Memory Accesses and Cacheability
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| /linux/arch/m68k/kernel/ |
| H A D | head.S | 215 * the cacheability of the kernel bits.
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| /linux/Documentation/ |
| H A D | memory-barriers.txt | 2989 Chapter 5: Memory Accesses and Cacheability
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| /linux/Documentation/translations/sp_SP/ |
| H A D | memory-barriers.txt | 3107 Capítulo 5: Memory Accesses and Cacheability
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