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Searched full:cacheability (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml118 cacheability attributes but is connected to a non-coherent
169 cacheability attributes but is connected to a non-coherent
/linux/arch/x86/include/asm/
H A Dagp.h12 * mappings with different cacheability attributes for the same
/linux/drivers/iommu/
H A Dmsm_iommu.h16 /* Cacheability attributes of MSM IOMMU mappings */
/linux/arch/sparc/include/asm/
H A Dswift.h21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S41 li r3,0x1200 /* enable i-fetch cacheability */
/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml240 The standard Ssccptr extension for main memory (cacheability and
558 The standard Ziccamoa extension for main memory (cacheability and
565 The standard Ziccif extension for main memory (cacheability and
572 The standard Zicclsm extension for main memory (cacheability and
/linux/include/linux/
H A Dio-pgtable.h84 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_meta.h277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h107 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
/linux/arch/riscv/
H A DKconfig625 that indicate the cacheability, idempotency, and ordering
/linux/drivers/irqchip/
H A Dirq-gic-v3-its.c3200 * remove the cacheability attributes as in its_cpu_init_lpis()
3226 * cacheability attributes as well. in its_cpu_init_lpis()
5318 * remove the cacheability attributes as in its_probe_one()
/linux/arch/mips/
H A DKconfig1142 # MIPS allows mixing "slightly different" Cacheability and Coherency
/linux/include/uapi/drm/
H A Di915_drm.h134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
/linux/tools/include/uapi/drm/
H A Di915_drm.h
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c2018 * Program cacheability overrides to not allocate cache in a6xx_llc_activate()
/linux/Documentation/
H A Dmemory-barriers.txt2989 Chapter 5: Memory Accesses and Cacheability
/linux/Documentation/translations/sp_SP/
H A Dmemory-barriers.txt3107 Capítulo 5: Memory Accesses and Cacheability