Searched full:cacheability (Results 1 – 25 of 28) sorted by relevance
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12 * mappings with different cacheability attributes for the same
15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
112 and cacheability attributes but are connected to a non-coherent205 cacheability attributes but is connected to a non-coherent
16 /* Cacheability attributes of MSM IOMMU mappings */
21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
41 li r3,0x1200 /* enable i-fetch cacheability */
225 /* MIPS cacheability is determined by page table. */ in pvr_mips_get_fw_addr_with_offset()
510 /* META cacheability is determined by address. */ in pvr_meta_get_fw_addr_with_offset()
277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
86 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
340 * Function Memory type Cacheability Cache hint
107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
606 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
145 * Thus it is expected to allow LLC cacheability to enable coherent
100 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
440 | API | Memory region type and cacheability |
564 that indicate the cacheability, idempotency, and ordering
3120 * remove the cacheability attributes as in its_cpu_init_lpis()3146 * cacheability attributes as well. in its_cpu_init_lpis()5168 * remove the cacheability attributes as in its_probe_one()
1109 # MIPS allows mixing "slightly different" Cacheability and Coherency
134 * MOCS indexes used for GPU surfaces, defining the cacheability of the144 * Cacheability and coherency controlled by the kernel automatically
1628 * Program cacheability overrides to not allocate cache in a6xx_llc_activate()
2330 * set on M7 processor. Compute the value of cacheability in paging_init()
2925 Chapter 5: Memory Accesses and Cacheability