| /linux/arch/powerpc/kernel/ |
| H A D | cacheinfo.c | 3 * Processor cache information made available to userspace via sysfs;
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
52 /* Allow for both [di]-cache-line-size and
53 * [di]-cache-block-size properties. According to the PowerPC
[all …]
|
| /linux/drivers/md/ |
| H A D | dm-cache-target.c | 11 #include "dm-cache-metadata.h"
13 #include "dm-cache-background-tracker.h"
25 #define DM_MSG_PREFIX "cache"
28 "A percentage of time allocated for copying to and/or from cache");
36 * cblock: index of a cache block
37 * promotion: movement of a block from origin to cache
38 * demotion: movement of a block from cache to origin
39 * migration: movement of a block between the origin and cache device,
241 * The block size of the device holding cache data must be
256 * dirty. If you lose the cache device you will lose data.
[all …]
|
| /linux/arch/riscv/boot/dts/sophgo/ |
| H A D | sg2042-cpus.dtsi | 265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
267 i-cache-sets = <512>;
268 d-cache-block-size = <64>;
269 d-cache-size = <65536>;
270 d-cache-sets = <512>;
271 next-level-cache = <&l2_cache0>;
290 i-cache-block-size = <64>;
291 i-cache-size = <65536>;
292 i-cache-sets = <512>;
[all …]
|
| /linux/fs/cachefiles/ |
| H A D | cache.c | 2 /* Manage high-level VFS aspects of a cache.
15 * Bring a cache online.
17 int cachefiles_add_cache(struct cachefiles_cache *cache) in cachefiles_add_cache() argument
28 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache()
33 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache()
37 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache()
39 /* look up the directory at the root of the cache */ in cachefiles_add_cache()
40 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache()
44 cache->mnt = path.mnt; in cachefiles_add_cache()
49 pr_warn("File cache on idmapped mounts not supported"); in cachefiles_add_cache()
[all …]
|
| H A D | daemon.c | 62 int (*handler)(struct cachefiles_cache *cache, char *args);
88 * Prepare a cache for caching.
92 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
104 /* allocate a cache record */ in cachefiles_daemon_open()
105 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
106 if (!cache) { in cachefiles_daemon_open()
111 mutex_init(&cache->daemon_mutex); in cachefiles_daemon_open()
112 init_waitqueue_head(&cache->daemon_pollwq); in cachefiles_daemon_open()
113 INIT_LIST_HEAD(&cache->volumes); in cachefiles_daemon_open()
114 INIT_LIST_HEAD(&cache->object_list); in cachefiles_daemon_open()
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z16/ |
| H A D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …on Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replace…
21 … request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for th…
42 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
49 …ade by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the L…
91 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
97 "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
98 …tory write to the Level-1 Data cache directory where the returned cache line was sourced from the …
104 "BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
105 …tory write to the Level-1 Data cache directory where the returned cache line was sourced from the …
[all …]
|
| /linux/arch/arm64/boot/dts/amazon/ |
| H A D | alpine-v3.dtsi | 28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&cluster0_l2>;
42 d-cache-size = <0x8000>;
43 d-cache-line-size = <64>;
44 d-cache-sets = <256>;
[all …]
|
| /linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-cpus.dtsi | 49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <256>;
55 l2-cache = <&L2_0>;
65 i-cache-size = <0xC000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
[all …]
|
| /linux/fs/ |
| H A D | mbcache.c | 16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
50 static inline struct hlist_bl_head *mb_cache_entry_head(struct mb_cache *cache, in mb_cache_entry_head() argument
53 return &cache->c_hash[hash_32(key, cache->c_bucket_bits)]; in mb_cache_entry_head()
58 * in cache
63 * mb_cache_entry_create - create entry in cache
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | mmu.json | 9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | cache.json | 23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59 "BriefDescription": "Demand data cache fills from extension memory.",
65 "BriefDescription": "Demand data cache fills from all types of data sources.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
[all …]
|
| /linux/Documentation/devicetree/bindings/cache/ |
| H A D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
[all …]
|
| H A D | socionext,uniphier-system-cache.yaml | 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
19 const: socionext,uniphier-system-cache
29 Interrupts can be used to notify the completion of cache operations.
35 cache-unified: true
37 cache-size: true
39 cache-sets: true
[all …]
|
| /linux/fs/squashfs/ |
| H A D | cache.c | 8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
49 * Look-up block in cache, and increment usage count. If not in cache, rea
53 squashfs_cache_get(struct super_block * sb,struct squashfs_cache * cache,u64 block,int length) squashfs_cache_get() argument
175 struct squashfs_cache *cache = entry->cache; squashfs_cache_put() local
197 squashfs_cache_delete(struct squashfs_cache * cache) squashfs_cache_delete() argument
227 struct squashfs_cache *cache = kzalloc(sizeof(*cache), GFP_KERNEL); squashfs_cache_init() local
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| H A D | cache.json | 111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
[all …]
|
| /linux/mm/ |
| H A D | swap_slots.c | 3 * Manage cache of swap slots to be used for and returned from
25 * The swap slots cache is protected by a mutex instead of
43 /* Serialize swap slots cache enable/disable operations */
104 /* if global pool of slot caches too low, deactivate cache */ in check_cache_active()
113 struct swap_slots_cache *cache; in alloc_swap_slot_cache()
127 cache = &per_cpu(swp_slots, cpu); in alloc_swap_slot_cache()
128 if (cache->slots) { in alloc_swap_slot_cache()
129 /* cache already allocated */ in alloc_swap_slot_cache()
137 if (!cache->lock_initialized) { in alloc_swap_slot_cache()
138 mutex_init(&cache in alloc_swap_slot_cache()
115 struct swap_slots_cache *cache; alloc_swap_slot_cache() local
171 struct swap_slots_cache *cache; drain_slots_cache_cpu() local
259 refill_swap_slots_cache(struct swap_slots_cache * cache) refill_swap_slots_cache() argument
274 struct swap_slots_cache *cache; free_swap_slot() local
308 struct swap_slots_cache *cache; folio_alloc_swap() local
[all...] |
| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j784s4.dtsi | 63 i-cache-size = <0xc000>;
64 i-cache-line-size = <64>;
65 i-cache-sets = <256>;
66 d-cache-size = <0x8000>;
67 d-cache-line-size = <64>;
68 d-cache-sets = <256>;
69 next-level-cache = <&L2_0>;
77 i-cache-size = <0xc000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
[all …]
|
| H A D | k3-am654.dtsi | 41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
43 i-cache-sets = <256>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
46 d-cache-sets = <128>;
47 next-level-cache = <&L2_0>;
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z13/ |
| H A D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
126 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
133 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
140 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
147 …ctory write to the Level-1 Data cache directory where the returned cache line was sourced from an …
[all …]
|
| /linux/Documentation/filesystems/caching/ |
| H A D | backend-api.rst | 4 Cache Backend API
7 The FS-Cache system provides an API by which actual caches can be supplied to
8 FS-Cache for it to then serve out to network filesystems and other interested
11 #include <linux/fscache-cache.h>.
17 Interaction with the API is handled on three levels: cache, volume and data
23 Cache cookie struct fscache_cache
28 Cookies are used to provide some filesystem data to the cache, manage state and
29 pin the cache during access in addition to acting as reference points for the
34 The cache backend and the network filesystem can both ask for cache cookies -
39 Cache Cookies
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l1d_cache.json | 4 "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line."
8 "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted."
12 "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache o
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | l1d_cache.json | 4 …cache refills caused by speculatively executed load or store operations that missed in the level 1…
8 …cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (…
12 …cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache an…
16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o…
20 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper…
24 … "Counts level 1 data cache accesses generated by store operations. This event also counts accesse…
28 …cache refills caused by speculatively executed load instructions where the memory read operation m…
32 …cache refills caused by speculatively executed store instructions where the memory write operation…
36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches…
40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou…
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z14/ |
| H A D | extended.json | 7 … cache where the line was originally in a Read-Only state in the cache but has been updated to be …
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
42 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t…
49 …ion Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replace…
56 …equest made by the instruction cache. Incremented by one for every TLB2 miss in progress for the L…
63 …te to the Level-1 Instruction cache directory where the returned cache line was sourced from the L…
105 …"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is…
112 …ectory write to the Level-1 Data cache directory where the returned cache line was sourced from an…
119 …licDescription": "A directory write to the Level-1 Data cache directory where the returned cache l…
[all …]
|
| /linux/drivers/acpi/acpica/ |
| H A D | utcache.c | 4 * Module Name: utcache - local cache allocation routines
21 * PARAMETERS: cache_name - Ascii name for the cache
23 * max_depth - Maximum depth of the cache (in objects)
24 * return_cache - Where the new cache object is returned
28 * DESCRIPTION: Create a cache object
36 struct acpi_memory_list *cache; in acpi_os_create_cache() local
44 /* Create the cache object */ in acpi_os_create_cache()
46 cache = acpi_os_allocate(sizeof(struct acpi_memory_list)); in acpi_os_create_cache()
47 if (!cache) { in acpi_os_create_cache()
51 /* Populate the cache object and return it */ in acpi_os_create_cache()
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 102 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event…
105 …cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this event…
108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
114 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin…
117 …2 cache write streaming mode. This event counts for each cycle where the core is in write streamin…
120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr…
123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry…
126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
[all …]
|