cache\-time\-ms (full) in projects: freebsd

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/freebsd/share/doc/papers/kerntune/
H A D	3.t	`61 time is long. 63 it may be advantageous to cache its results, 73 that begins to dominate execution time. 91 Despite the long period of time that elapsed 113 We find that our general time sharing systems do about 117 representing 40% of the time processing system calls, 126 part time % of kernel 128 self 14.3 ms/call 11.3% 129 child 9.9 ms/call 7.9% 131 total 24.2 ms/call 19.2% [all …]`
/freebsd/share/doc/papers/sysperf/
H A D	4.t	49 chosen to optimize running time at the expense of memory. 52 Decreases in the running time of the system may be unnoticeable 60 of the time in the system was spent in the 62 translating path names to inodes\u\s-21\s0\d\. 64 \ \u\s-21\s0\d Inode is an abbreviation for ``Index node''. 84 Changing directories invalidates the cache, as 90 $N$ files, search time decreases from $O ( N sup 2 )$ to $O(N)$. 95 The cost of the cache is about 20 lines of code 101 cache we ran ``ls \-l'' 103 Before the per-process cache this command [all …]
H A D	3.t	51 on one machine, a VAX-11/780 with eight megabytes of memory.\** 58 person-to-person telephone messages to per-organization distribution 83 pseudo-terminal handler in addition to the local hardware terminal 98 Despite the long period of time that elapsed 109 the ratio of user to system time had increased from 113 Micro-operation benchmarks 117 programs was constructed and run on a VAX-11/750 with 4.5 megabytes 144 text segment; unfortunately time did not permit running additional tests. 159 pipeself4 send 10,000 4-byte messages to yourself 160 pipeself512 send 10,000 512-byte messages to yourself [all …]
H A D	2.t	54 out at 25-35 tps in practice), and the user cpu utilization (us) should 60 be non-zero). It is healthy for the paging demon to free pages when 70 is overloaded or imbalanced. If you have several non-dma 72 that are doing high-speed non-buffered input/output, then the system 73 time may go high (60-80% or higher). 74 It is often possible to pin down the cause of high system time by 94 It also gives the percentage of time the system has 102 Also, every 100 ms, 118 non-zero average seek times. Most modern disk drives should 119 exhibit an average seek time of 25-35 ms. [all …]
/freebsd/sys/contrib/openzfs/man/man4/
H A D	zfs.4	`9 .\" usr/src/OPENSOLARIS.LICENSE or https://opensource.org/licenses/CDDL-1.0. 31 .Bl -tag -width Ds 33 Maximum size in bytes of the dbuf cache. 37 The behavior of the dbuf cache and its associated settings 43 Maximum size in bytes of the metadata dbuf cache. 47 The behavior of the metadata dbuf cache and its associated settings 63 Set the size of the dbuf cache 68 Set the size of the dbuf metadata cache 73 Set the size of the mutex array for the dbuf cache. 102 Turbo L2ARC warm-up. [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	frontend.json	38 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins… 48 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin… 58 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).… 68 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (… 73 "BriefDescription": "MS decode starts", 78 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	frontend.json	46 …"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for ins… 58 …Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache lin… 70 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit).… 82 …Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (… 87 "BriefDescription": "MS decode starts", 94 …MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSRO…
/freebsd/sys/contrib/device-tree/Bindings/power/supply/
H A D	maxim,ds2760.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sebastian Reichel <sre@kernel.org> 13 The ds2760 is a w1 slave device and must hence have its sub-node in 17 - $ref: power-supply.yaml# 23 maxim,pmod-enabled: 29 maxim,cache-time-ms: 31 Time im milliseconds to cache the data for. 32 When this time expires, the values are read again from the hardware. [all …]`
H A D	maxim,ds2760.txt	`4 The ds2760 is a w1 slave device and must hence have its sub-node in DT 11 - compatible: must be "maxim,ds2760" 14 - power-supplies: Refers to one or more power supplies connected to 16 - maxim,pmod-enabled: This boolean property enables the DS2760 to enter 20 - maxim,cache-time-ms: Time im milliseconds to cache the data for. When 21 this time expires, the values are read again from 23 - rated-capacity-microamp-hours: 26 non-volatile chip memory is used.`
/freebsd/lib/libpmc/
H A D	pmc.sandybridgexeon.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 54 determined at run time by calling 59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 61 .%N "Order Number: 253669-043US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 89 Configure the Off-core Response bits. 90 .Bl -tag -width indent 127 M-state initial lookup stat in L3. [all …]`
H A D	pmc.sandybridge.3	`45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 57 determined at run time by calling 62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" 64 .%N "Order Number: 253669-039US" 73 .Bl -column "PMC_CAP_INTERRUPT" "Support" 90 .Bl -tag -width indent 92 Configure the Off-core Response bits. 93 .Bl -tag -width indent 130 M-state initial lookup stat in L3. [all …]`
H A D	pmc.atomsilvermont.3	45 .Bl -tag -width "Li PMC_CLASS_IAP" 47 Fixed-function counters that count only one hardware event per counter. 54 determined at run time by calling 59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual" 61 .%N "Order Number 325462-050US" 70 .Bl -column "PMC_CAP_INTERRUPT" "Support" 87 .Bl -tag -width indent 95 Configure the PMC to count the number of de-asserted to asserted 121 Events that require core-specificity to be specified use a 127 .Bl -tag -width indent [all …]
/freebsd/sys/contrib/openzfs/man/man8/
H A D	zinject.8	`9 .\" or https://opensource.org/licenses/CDDL-1.0. 24 .\" lint-ok: WARNING: sections out of conventional order: Sh SYNOPSIS 40 .Bl -tag -width Ds 85 For example, with a single lane delay of 10 ms 88 at a time with each request taking 10 ms to complete. 89 So, if only a single request is submitted every 10 ms, the 90 average latency will be 10 ms; but if more than one request 91 is submitted every 10 ms, th [all...]`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	frontend.json	9 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 35 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 65 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 86 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 95 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 101 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	9 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 14 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 27 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 47 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 62 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 83 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 92 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 98 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	frontend.json	8 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 55 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	8 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 55 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	frontend.json	8 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 55 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 75 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 88 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/freebsd/contrib/unbound/util/
H A D	rtt.c	2 * util/rtt.c - UDP round trip time estimator for resend timeouts. 56 int rto = rtt->srtt + 4rtt->rttvar; in calc_rto() 67 rtt->srtt = 0; in rtt_init() 68 rtt->rttvar = UNKNOWN_SERVER_NICENESS/4; in rtt_init() 69 rtt->rto = calc_rto(rtt); in rtt_init() 77 return rtt->rto; in rtt_timeout() 83 if(calc_rto(rtt) != rtt->rto) { in rtt_unclamped() 85 return rtt->rto; in rtt_unclamped() 88 return rtt->srtt + 4rtt->rttvar; in rtt_unclamped() 92 rtt_update(struct rtt_info* rtt, int ms) in rtt_update() argument [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	frontend.json	9 … number of times the front-end is resteered when it finds a branch instruction in a fetch line. Th… 15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 35 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 65 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … 86 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 95 …"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 101 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", [all …]
/freebsd/share/man/man4/
H A D	tcp.4	`3 .\" Copyright (c) 2010-2011 The FreeBSD Foundation 50 protocol provides reliable, flow-controlled, two-way 52 It is a byte-stream protocol used to 58 Internet address format and, in addition, provides a per-host 106 at this time; if the port is not specified, the system will assign one. 119 .Bl -tag -width ".Dv TCP_FUNCTION_BLK" 122 by passing the read-only option 136 bandwidth-controlled window space. 161 For passively-created sockets, the 167 but that fall back to using a non-TFO [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/knightslanding/
H A D	pipeline.json	181 …time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th… 205 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last … 233 …"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for an… 241 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the allo… 250 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is e… 259 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATsta… 267 …"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB … 309 …"BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Ea… 327 …"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue becaus… 335 …"BriefDescription": "Counts the number of occurences a retired store that is a cache line split. E… [all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/asan/
H A D	asan_allocator.cpp	1 //===-- asan_allocator.cpp ------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 // Implementation of ASan's memory allocator, 2-nd version. 15 //===----------------------------------------------------------------------===// 49 u32 res = Log2(rz_size) - 4; in RZSize2Log() 74 // L -- left redzone words (0 or more bytes) 75 // H -- ChunkHeader (16 bytes), which is also a part of the left redzone. 76 // U -- user memory. 77 // R -- right redzone (0 or more bytes) [all …]
/freebsd/sys/netinet/tcp_stacks/
H A D	tcp_bbr.h	1 /- 2 Copyright (c) 2016-2020 Netflix, Inc. 29 #define BBR_INITIAL_RTO 1000000 /* 1 second in micro-seconds / 39 #define BBR_TLP 0x0080 / segment sent as tail-loss-probe / 43 totaled into bbr->rc_ctl.rc_lost 56 * cache line (unfortunately). For now there is 62 TAILQ_ENTRY(bbr_sendmap) r_tnext; /* Time of tmit based next / 69 uint32_t r_del_time; / The time of the last delivery update / 70 uint8_t r_rtr_cnt:4, / Retran count, index this -1 to get time 78 r_is_smallmap:1,/* Was logged as a small-map send-map item */ [all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A D	idle-states.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 - Anup Patel <anup@brainfault.org> 15 1 - Introduction 18 ARM and RISC-V systems contain HW capable of managing power consumption 19 dynamically, where cores can be put in different low-power states (ranging 22 run-time, can be specified through device tree bindings representing the [all …]

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