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/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …nslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a r…
17 "Unit": "CPU-M-CF",
21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …nslation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a r…
17 "Unit": "CPU-M-CF",
21 …s for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
114 …tion": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetche…
117Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
144Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
147Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
150Level 3 cache write streaming mode. This event counts for each cycle where the core is in write-st…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …on": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a …
[all …]
H A Dbasic.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
120 …on": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetch…
123Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
126Level 2 cache write streaming mode. This event counts for each cycle where the core is in write-st…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 … directory write to the Level-1 Data cache directory where the returned cache line was sourced fro…
24 "Unit": "CPU-M-CF",
28 …ectory write to the Level-1 Instruction cache directory where the returned cache line was sourced …
31 "Unit": "CPU-M-CF",
35 … "A directory write to the Level-1 Data cache directory where the returned cache line was sourced …
[all …]
H A Dbasic.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been up…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …n": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Instruction Cache directory where the returned cache line was so…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
[all …]
H A Dbasic.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dl2_cache.json4level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru…
12-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP…
20level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t…
40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio…
44cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
[all …]
H A Dl1d_cache.json4level 1 data cache refills caused by speculatively executed load or store operations that missed i…
8level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the …
12-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache
16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o…
20 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper…
24 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts …
28level 1 data cache refills caused by speculatively executed load instructions where the memory rea…
32level 1 data cache refills caused by speculatively executed store instructions where the memory wr…
36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches…
40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou…
[all …]
H A Dmetrics.json14 …"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((…
60 …"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)…
100level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives …
102 "ScaleUnit": "1per cache access"
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
130 "ScaleUnit": "1per cache access"
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dl2_cache.json4level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …ts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instru…
12-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP…
20level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …licDescription": "Counts evictions from the level 2 cache because of a line being allocated into t…
40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio…
44cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
H A Dl1d_cache.json4level 1 data cache refills caused by speculatively executed load or store operations that missed i…
8level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the …
12-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache
16 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper…
20 …ption": "Counts level 1 data cache accesses generated by store operations. This event also counts …
24level 1 data cache refills caused by speculatively executed load instructions where the memory rea…
28level 1 data cache refills caused by speculatively executed store instructions where the memory wr…
32 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches…
36 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou…
40 … dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. Thi…
[all …]
H A Dmetrics.json89level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives …
91 "ScaleUnit": "1per cache access"
96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
103 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
117level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
119 "ScaleUnit": "1per cache access"
124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
131level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
[all …]
/linux/arch/powerpc/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …directory write to the Level-1 Instruction Cache directory where the returned cache line was sourc…
10 "Unit": "CPU-M-CF",
14 …"A directory write to the Level-1 Data Cache directory where the installed cache line was sourced …
17 "Unit": "CPU-M-CF",
21Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 ca…
24 "Unit": "CPU-M-CF",
28Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that…
31 "Unit": "CPU-M-CF",
35Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cach…
[all …]
H A Dbasic.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u…
31 "Unit": "CPU-M-CF",
34 "BriefDescription": "Level-1 D-Cache Directory Write Count",
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx943.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #address-cells = <1>;
11 #size-cells = <0>;
13 idle-states {
14 entry-method = "psci";
16 cpu_pd_wait: cpu-pd-wait {
17 compatible = "arm,idle-state";
18 arm,psci-suspend-param = <0x0010033>;
19 local-timer-stop;
20 entry-latency-us = <1000>;
[all …]
/linux/Documentation/devicetree/bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]

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