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/linux/arch/powerpc/kernel/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
[all …]
/linux/drivers/md/
H A Ddm-cache-target.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dm-bio-prison-v2.h"
10 #include "dm-bio-record.h"
11 #include "dm-cache-metadata.h"
12 #include "dm-io-tracker.h"
13 #include "dm-cache-background-tracker.h"
15 #include <linux/dm-io.h>
16 #include <linux/dm-kcopyd.h>
25 #define DM_MSG_PREFIX "cache"
28 "A percentage of time allocated for copying to and/or from cache");
[all …]
/linux/fs/netfs/
H A Dfscache_cache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* FS-Cache cache handling
8 #define FSCACHE_DEBUG_LEVEL CACHE
22 * Allocate a cache cookie.
26 struct fscache_cache *cache; in fscache_alloc_cache() local
28 cache = kzalloc(sizeof(*cache), GFP_KERNEL); in fscache_alloc_cache()
29 if (cache) { in fscache_alloc_cache()
31 cache->name = kstrdup(name, GFP_KERNEL); in fscache_alloc_cache()
32 if (!cache->name) { in fscache_alloc_cache()
33 kfree(cache); in fscache_alloc_cache()
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
267 i-cache-sets = <512>;
[all …]
H A Dsg2044-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
[all …]
/linux/fs/cachefiles/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Manage high-level VFS aspects of a cache.
15 * Bring a cache online.
17 int cachefiles_add_cache(struct cachefiles_cache *cache) in cachefiles_add_cache() argument
28 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache()
33 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache()
37 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache()
39 /* look up the directory at the root of the cache */ in cachefiles_add_cache()
40 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache()
44 cache->mnt = path.mnt; in cachefiles_add_cache()
[all …]
H A Ddaemon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 int (*handler)(struct cachefiles_cache *cache, char *args);
88 * Prepare a cache for caching.
92 struct cachefiles_cache *cache; in cachefiles_daemon_open() local
98 return -EPERM; in cachefiles_daemon_open()
102 return -EBUSY; in cachefiles_daemon_open()
104 /* allocate a cache record */ in cachefiles_daemon_open()
105 cache = kzalloc(sizeof(struct cachefiles_cache), GFP_KERNEL); in cachefiles_daemon_open()
106 if (!cache) { in cachefiles_daemon_open()
108 return -ENOMEM; in cachefiles_daemon_open()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …lation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a rep…
17 "Unit": "CPU-M-CF",
21 …or a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress fo…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #address-cells = <0x1>;
6 #size-cells = <0x0>;
8 cpu-map {
45 compatible = "arm,cortex-a57";
47 enable-method = "psci";
49 i-cache-size = <0xC000>;
50 i-cache-line-size = <64>;
51 i-cache-sets = <256>;
52 d-cache-size = <0x8000>;
[all …]
/linux/fs/
H A Dmbcache.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * Mbcache is a simple key-value store. Keys need not be unique, however
13 * key-value pairs are expected to be unique (we use this fact in
16 * Ext2 and ext4 use this cache for deduplication of extended attribute blocks.
21 * identifies a cache entry.
24 * and a special "delete entry with given key-value pair" operation. Fixed
33 /* Maximum entries in cache to avoid degrading hash too much */
38 /* Number of entries in cache */
41 /* Work for shrinking when the cache has too many entries */
47 static unsigned long mb_cache_shrink(struct mb_cache *cache,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx943.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #address-cells = <1>;
11 #size-cells = <0>;
13 idle-states {
14 entry-method = "psci";
16 cpu_pd_wait: cpu-pd-wait {
17 compatible = "arm,idle-state";
18 arm,psci-suspend-param = <0x0010033>;
19 local-timer-stop;
20 entry-latency-us = <1000>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dmmu.json9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
[all …]
/linux/Documentation/devicetree/bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
[all …]
H A Dsocionext,uniphier-system-cache.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
/linux/fs/squashfs/
H A Dcache.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Squashfs - a compressed read only filesystem for Linux
8 * cache.c
15 * This file implements a generic cache implementation used for both caches,
16 * plus functions layered ontop of the generic cache implementation to
19 * To avoid out of memory and fragmentation issues with vmalloc the cache
22 * It should be noted that the cache is not used for file datablocks, these
23 * are decompressed and cached in the page-cache in the normal way. The
24 * cache is only used to temporarily cache fragment and metadata blocks
29 * have been packed with it, these because of locality-of-reference may be read
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which…
117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event …
123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c…
141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami…
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
11 #include "k3-j784s4-j742s2-common.dtsi"
18 #address-cells = <1>;
19 #size-cells = <0>;
20 cpu-map {
59 compatible = "arm,cortex-a72";
62 enable-method = "psci";
63 i-cache-size = <0xc000>;
64 i-cache-line-size = <64>;
[all …]
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dcache.json5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59 "BriefDescription": "Demand data cache fills from extension memory.",
[all …]
/linux/scripts/gendwarfksyms/
H A Ddwarf.c1 // SPDX-License-Identifier: GPL-2.0
14 #define KABI_PREFIX_LEN (sizeof(KABI_PREFIX) - 1)
16 #define KABI_RESERVED_PREFIX_LEN (sizeof(KABI_RESERVED_PREFIX) - 1)
18 #define KABI_RENAMED_PREFIX_LEN (sizeof(KABI_RENAMED_PREFIX) - 1)
20 #define KABI_IGNORED_PREFIX_LEN (sizeof(KABI_IGNORED_PREFIX) - 1)
37 /* Line breaks and indentation for pretty-printing */
38 static void process_linebreak(struct die *cache, int n) in process_linebreak() argument
42 die_map_add_linebreak(cache, n); in process_linebreak()
98 state->sym = symbol_get(get_symbol_name(die)); in match_export_symbol()
101 if (!state->sym && source != die) in match_export_symbol()
[all …]
/linux/Documentation/filesystems/caching/
H A Dbackend-api.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Cache Backend API
7 The FS-Cache system provides an API by which actual caches can be supplied to
8 FS-Cache for it to then serve out to network filesystems and other interested
11 #include <linux/fscache-cache.h>.
17 Interaction with the API is handled on three levels: cache, volume and data
23 Cache cookie struct fscache_cache
28 Cookies are used to provide some filesystem data to the cache, manage state and
29 pin the cache during access in addition to acting as reference points for the
34 The cache backend and the network filesystem can both ask for cache cookies -
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated…
10 "Unit": "CPU-M-CF",
14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace…
17 "Unit": "CPU-M-CF",
21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
[all …]
/linux/drivers/acpi/acpica/
H A Dutcache.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utcache - local cache allocation routines
6 * Copyright (C) 2000 - 2025, Intel Corp.
21 * PARAMETERS: cache_name - Ascii name for the cache
22 * object_size - Size of each cached object
23 * max_depth - Maximum depth of the cache (in objects)
24 * return_cache - Where the new cache object is returned
28 * DESCRIPTION: Create a cache object
36 struct acpi_memory_list *cache; in acpi_os_create_cache() local
44 /* Create the cache object */ in acpi_os_create_cache()
[all …]

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