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/linux/tools/perf/pmu-events/
H A D	empty-pmu-events.c	`1 /* SPDX-License-Identifier: GPL-2.0 / 4 #include <pmu-events/pmu-events.h> 20 / clang-format off */ 25 "l1-dcache\000legacy cache\000Level 1 data cache read accesses\000legacy-cach [all...]`
/linux/arch/powerpc/kernel/
H A D	cacheinfo.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Processor cache information made available to userspace via sysfs; 27 /* per-cpu object for tracking: 28 * - a "cache" kobject for the top-level directory 29 * - a list of "index" objects representing the cpu's local cache hierarchy 32 struct kobject kobj; / bare (not embedded) kobject for cache 37 /* "index" object: each cpu's cache directory has an index 38 * subdirectory corresponding to a cache object associated with the 44 struct cache cache; member 48 cache type */ [all …]
/linux/fs/netfs/
H A D	fscache_cache.c	`1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* FS-Cache cache handling 8 #define FSCACHE_DEBUG_LEVEL CACHE 22 * Allocate a cache cookie. 26 struct fscache_cache cache; in fscache_alloc_cache() local 28 cache = kzalloc_obj(cache); in fscache_alloc_cache() 29 if (cache) { in fscache_alloc_cache() 31 cache->name = kstrdup(name, GFP_KERNEL); in fscache_alloc_cache() 32 if (!cache->name) { in fscache_alloc_cache() 33 kfree(cache); in fscache_alloc_cache() [all …]`
/linux/fs/cachefiles/
H A D	cache.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Manage high-level VFS aspects of a cache. 15 * Bring a cache online. 17 int cachefiles_add_cache(struct cachefiles_cache cache) in cachefiles_add_cache() argument 28 cache_cookie = fscache_acquire_cache(cache->tag); in cachefiles_add_cache() 33 ret = cachefiles_get_security_ID(cache); in cachefiles_add_cache() 37 cachefiles_begin_secure(cache, &saved_cred); in cachefiles_add_cache() 39 / look up the directory at the root of the cache */ in cachefiles_add_cache() 40 ret = kern_path(cache->rootdirname, LOOKUP_DIRECTORY, &path); in cachefiles_add_cache() 44 cache->mnt = path.mnt; in cachefiles_add_cache() [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 10 "Unit": "CPU-M-CF", 14 …lation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a rep… 17 "Unit": "CPU-M-CF", 21 …or a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress fo… 24 "Unit": "CPU-M-CF", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/arch/arm64/boot/dts/amd/
H A D	amd-seattle-cpus.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 8 cpu-map { 45 compatible = "arm,cortex-a57"; 47 enable-method = "psci"; 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; [all …]`
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	mmu.json	9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry", 12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry" 15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry", 18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry" 21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry", 24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry" 27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry", 30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry" 33 "PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry", 36 "BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry" [all …]
/linux/Documentation/devicetree/bindings/cache/
H A D	freescale-l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 8 - compatible : Should include one of the following: 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" [all …]`
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 10 "Unit": "CPU-M-CF", 14 …lation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a rep… 17 "Unit": "CPU-M-CF", 21 …or a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress fo… 24 "Unit": "CPU-M-CF", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	cache.json	111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… [all …]
/linux/arch/arm64/boot/dts/ti/
H A D	k3-j784s4.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 7 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 11 #include "k3-j784s4-j742s2-common.dtsi" 18 #address-cells = <1>; 19 #size-cells = <0>; 20 cpu-map { 59 compatible = "arm,cortex-a72"; 62 enable-method = "psci"; 63 i-cache-size = <0xc000>; 64 i-cache-line-size = <64>; [all …]`
H A D	k3-am654.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; [all …]`
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 10 "Unit": "CPU-M-CF", 14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 17 "Unit": "CPU-M-CF", 21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	cache.json	5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all… 11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har… 17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all… 23 "BriefDescription": "Demand data cache fills from local L2 cache.", 29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.", 35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the… 41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.", 47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d… 53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa… 59 "BriefDescription": "Demand data cache fills from extension memory.", [all …]
/linux/Documentation/filesystems/caching/
H A D	backend-api.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 Cache Backend API 7 The FS-Cache system provides an API by which actual caches can be supplied to 8 FS-Cache for it to then serve out to network filesystems and other interested 11 #include <linux/fscache-cache.h>. 17 Interaction with the API is handled on three levels: cache, volume and data 23 Cache cookie struct fscache_cache 28 Cookies are used to provide some filesystem data to the cache, manage state and 29 pin the cache during access in addition to acting as reference points for the 34 The cache backend and the network filesystem can both ask for cache cookies - [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 10 "Unit": "CPU-M-CF", 14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace… 17 "Unit": "CPU-M-CF", 21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… [all …]
/linux/scripts/gendwarfksyms/
H A D	dwarf.c	1 // SPDX-License-Identifier: GPL-2.0 14 #define KABI_PREFIX_LEN (sizeof(KABI_PREFIX) - 1) 16 #define KABI_RESERVED_PREFIX_LEN (sizeof(KABI_RESERVED_PREFIX) - 1) 18 #define KABI_RENAMED_PREFIX_LEN (sizeof(KABI_RENAMED_PREFIX) - 1) 20 #define KABI_IGNORED_PREFIX_LEN (sizeof(KABI_IGNORED_PREFIX) - 1) 37 /* Line breaks and indentation for pretty-printing / 38 static void process_linebreak(struct die cache, int n) in process_linebreak() argument 42 die_map_add_linebreak(cache, in process_linebreak() 147 is_kabi_definition(struct die * cache,Dwarf_Die * die) is_kabi_definition() argument 163 process(struct die * cache,const char * s) process() argument 183 process_fmt(struct die * cache,const char * fmt,...) process_fmt() argument 197 update_fqn(struct die * cache,Dwarf_Die * die) update_fqn() argument 210 process_fqn(struct die * cache,Dwarf_Die * die) process_fqn() argument 266 process_die_container(struct state * state,struct die * cache,Dwarf_Die * die,die_callback_t func,die_match_callback_t match) process_die_container() argument 300 process_type_attr(struct state * state,struct die * cache,Dwarf_Die * die) process_type_attr() argument 314 process_list_comma(struct state * state,struct die * cache) process_list_comma() argument 325 __process_list_type(struct state * state,struct die * cache,Dwarf_Die * die,const char * type) __process_list_type() argument 411 process_array_type(struct state * state,struct die * cache,Dwarf_Die * die) process_array_type() argument 425 __process_subroutine_type(struct state * state,struct die * cache,Dwarf_Die * die,const char * type) __process_subroutine_type() argument 442 process_subroutine_type(struct state * state,struct die * cache,Dwarf_Die * die) process_subroutine_type() argument 448 process_variant_type(struct state * state,struct die * cache,Dwarf_Die * die) process_variant_type() argument 461 process_variant_part_type(struct state * state,struct die * cache,Dwarf_Die * die) process_variant_part_type() argument 667 ___process_structure_type(struct state * state,struct die * cache,Dwarf_Die * die) ___process_structure_type() argument 690 __process_structure_type(struct state * state,struct die * cache,Dwarf_Die * die,const char * type,die_callback_t process_func,die_match_callback_t match_func) __process_structure_type() argument 749 process_enumerator_type(struct state * state,struct die * cache,Dwarf_Die * die) process_enumerator_type() argument 777 process_enumeration_type(struct state * state,struct die * cache,Dwarf_Die * die) process_enumeration_type() argument 784 process_base_type(struct state * state,struct die * cache,Dwarf_Die * die) process_base_type() argument 794 process_unspecified_type(struct state * state,struct die * cache,Dwarf_Die * die) process_unspecified_type() argument 804 process_cached(struct state * state,struct die * cache,Dwarf_Die * die) process_cached() argument 868 struct die cache; process_type() local 961 struct die cache; get_symbol_cache() local 975 struct die cache; process_symbol() local 990 __process_subprogram(struct state state,struct die * cache,Dwarf_Die * die) __process_subprogram() argument 1002 __process_variable(struct state * state,struct die * cache,Dwarf_Die * die) __process_variable() argument 1040 process_exported_symbols(struct state * unused,struct die * cache,Dwarf_Die * die) process_exported_symbols() argument 1106 struct die *cache; resolve_fqns() local [all...]
/linux/fs/btrfs/
H A D	lru_cache.c	1 // SPDX-License-Identifier: GPL-2.0 8 * Initialize a cache object. 10 * @cache: The cache. 11 * @max_size: Maximum size (number of entries) for the cache. 13 * trim the cache in that case. 15 void btrfs_lru_cache_init(struct btrfs_lru_cache *cache, unsigned int max_size) in btrfs_lru_cache_init() argument 17 INIT_LIST_HEAD(&cache->lru_list); in btrfs_lru_cache_init() 18 mt_init(&cache->entries); in btrfs_lru_cache_init() 19 cache->size = 0; in btrfs_lru_cache_init() 20 cache->max_size = max_size; in btrfs_lru_cache_init() [all …]
/linux/arch/arm64/boot/dts/marvell/
H A D	armada-ap806-quad.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 17 compatible = "arm,cortex-a72"; 19 enable-method = "psci"; 20 #cooling-cells = <2>; 22 i-cache-size = <0xc000>; 23 i-cache-line-size = <64>; 24 i-cache-sets = <256>; [all …]`
H A D	armada-ap807-quad.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap807.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 17 compatible = "arm,cortex-a72"; 19 enable-method = "psci"; 20 #cooling-cells = <2>; 22 i-cache-size = <0xc000>; 23 i-cache-line-size = <64>; 24 i-cache-sets = <256>; [all …]`
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A D	l1d_cache.json	4 …cache refills caused by speculatively executed load or store operations that missed in the level 1… 8 …cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (… 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 16 …"PublicDescription": "Counts cache line refills into the level 1 data cache from any memory read o… 20 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper… 24 … "Counts level 1 data cache accesses generated by store operations. This event also counts accesse… 28 …cache refills caused by speculatively executed load instructions where the memory read operation m… 32 …cache refills caused by speculatively executed store instructions where the memory write operation… 36 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 40 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 108 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 111 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 114 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 117 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 120 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 123 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 126 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each … 132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e… [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 10 "Unit": "CPU-M-CF", 14 …ranslation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replace… 17 "Unit": "CPU-M-CF", 21 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l1d_cache.json	4 …cache refills caused by speculatively executed load or store operations that missed in the level 1… 8 …cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (… 12 …-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache… 16 …"PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load oper… 20 … "Counts level 1 data cache accesses generated by store operations. This event also counts accesse… 24 …cache refills caused by speculatively executed load instructions where the memory read operation m… 28 …cache refills caused by speculatively executed store instructions where the memory write operation… 32 …"PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches… 36 …"PublicDescription": "Counts level 1 data cache refills for which the cache line data came from ou… 40 … dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. Thi… [all …]

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