Lines Matching +full:cache +full:-
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
22 d-cache-size = <65536>;
23 d-cache-sets = <512>;
25 mmu-type = "riscv,sv48";
26 next-level-cache = <&l2_cache0>;
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cboz-block-size = <64>;
43 cpu0_intc: interrupt-controller {
44 compatible = "riscv,cpu-intc";
45 interrupt-controller;
46 #interrupt-cells = <1>;
53 i-cache-block-size = <64>;
54 i-cache-size = <65536>;
55 i-cache-sets = <512>;
56 d-cache-block-size = <64>;
57 d-cache-size = <65536>;
58 d-cache-sets = <512>;
60 mmu-type = "riscv,sv48";
61 next-level-cache = <&l2_cache0>;
63 riscv,isa-base = "rv64i";
64 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
75 riscv,cbom-block-size = <64>;
76 riscv,cboz-block-size = <64>;
78 cpu1_intc: interrupt-controller {
79 compatible = "riscv,cpu-intc";
80 interrupt-controller;
81 #interrupt-cells = <1>;
88 i-cache-block-size = <64>;
89 i-cache-size = <65536>;
90 i-cache-sets = <512>;
91 d-cache-block-size = <64>;
92 d-cache-size = <65536>;
93 d-cache-sets = <512>;
95 mmu-type = "riscv,sv48";
96 next-level-cache = <&l2_cache0>;
98 riscv,isa-base = "rv64i";
99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
110 riscv,cbom-block-size = <64>;
111 riscv,cboz-block-size = <64>;
113 cpu2_intc: interrupt-controller {
114 compatible = "riscv,cpu-intc";
115 interrupt-controller;
116 #interrupt-cells = <1>;
123 i-cache-block-size = <64>;
124 i-cache-size = <65536>;
125 i-cache-sets = <512>;
126 d-cache-block-size = <64>;
127 d-cache-size = <65536>;
128 d-cache-sets = <512>;
130 mmu-type = "riscv,sv48";
131 next-level-cache = <&l2_cache0>;
133 riscv,isa-base = "rv64i";
134 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
145 riscv,cbom-block-size = <64>;
146 riscv,cboz-block-size = <64>;
148 cpu3_intc: interrupt-controller {
149 compatible = "riscv,cpu-intc";
150 interrupt-controller;
151 #interrupt-cells = <1>;
158 i-cache-block-size = <64>;
159 i-cache-size = <65536>;
160 i-cache-sets = <512>;
161 d-cache-block-size = <64>;
162 d-cache-size = <65536>;
163 d-cache-sets = <512>;
165 mmu-type = "riscv,sv48";
166 next-level-cache = <&l2_cache1>;
168 riscv,isa-base = "rv64i";
169 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
180 riscv,cbom-block-size = <64>;
181 riscv,cboz-block-size = <64>;
183 cpu4_intc: interrupt-controller {
184 compatible = "riscv,cpu-intc";
185 interrupt-controller;
186 #interrupt-cells = <1>;
193 i-cache-block-size = <64>;
194 i-cache-size = <65536>;
195 i-cache-sets = <512>;
196 d-cache-block-size = <64>;
197 d-cache-size = <65536>;
198 d-cache-sets = <512>;
200 mmu-type = "riscv,sv48";
201 next-level-cache = <&l2_cache1>;
203 riscv,isa-base = "rv64i";
204 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
215 riscv,cbom-block-size = <64>;
216 riscv,cboz-block-size = <64>;
218 cpu5_intc: interrupt-controller {
219 compatible = "riscv,cpu-intc";
220 interrupt-controller;
221 #interrupt-cells = <1>;
228 i-cache-block-size = <64>;
229 i-cache-size = <65536>;
230 i-cache-sets = <512>;
231 d-cache-block-size = <64>;
232 d-cache-size = <65536>;
233 d-cache-sets = <512>;
235 mmu-type = "riscv,sv48";
236 next-level-cache = <&l2_cache1>;
238 riscv,isa-base = "rv64i";
239 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
250 riscv,cbom-block-size = <64>;
251 riscv,cboz-block-size = <64>;
253 cpu6_intc: interrupt-controller {
254 compatible = "riscv,cpu-intc";
255 interrupt-controller;
256 #interrupt-cells = <1>;
263 i-cache-block-size = <64>;
264 i-cache-size = <65536>;
265 i-cache-sets = <512>;
266 d-cache-block-size = <64>;
267 d-cache-size = <65536>;
268 d-cache-sets = <512>;
270 mmu-type = "riscv,sv48";
271 next-level-cache = <&l2_cache1>;
273 riscv,isa-base = "rv64i";
274 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
285 riscv,cbom-block-size = <64>;
286 riscv,cboz-block-size = <64>;
288 cpu7_intc: interrupt-controller {
289 compatible = "riscv,cpu-intc";
290 interrupt-controller;
291 #interrupt-cells = <1>;
298 i-cache-block-size = <64>;
299 i-cache-size = <65536>;
300 i-cache-sets = <512>;
301 d-cache-block-size = <64>;
302 d-cache-size = <65536>;
303 d-cache-sets = <512>;
305 mmu-type = "riscv,sv48";
306 next-level-cache = <&l2_cache2>;
308 riscv,isa-base = "rv64i";
309 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
320 riscv,cbom-block-size = <64>;
321 riscv,cboz-block-size = <64>;
323 cpu8_intc: interrupt-controller {
324 compatible = "riscv,cpu-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
333 i-cache-block-size = <64>;
334 i-cache-size = <65536>;
335 i-cache-sets = <512>;
336 d-cache-block-size = <64>;
337 d-cache-size = <65536>;
338 d-cache-sets = <512>;
340 mmu-type = "riscv,sv48";
341 next-level-cache = <&l2_cache2>;
343 riscv,isa-base = "rv64i";
344 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
355 riscv,cbom-block-size = <64>;
356 riscv,cboz-block-size = <64>;
358 cpu9_intc: interrupt-controller {
359 compatible = "riscv,cpu-intc";
360 interrupt-controller;
361 #interrupt-cells = <1>;
368 i-cache-block-size = <64>;
369 i-cache-size = <65536>;
370 i-cache-sets = <512>;
371 d-cache-block-size = <64>;
372 d-cache-size = <65536>;
373 d-cache-sets = <512>;
375 mmu-type = "riscv,sv48";
376 next-level-cache = <&l2_cache2>;
378 riscv,isa-base = "rv64i";
379 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
390 riscv,cbom-block-size = <64>;
391 riscv,cboz-block-size = <64>;
393 cpu10_intc: interrupt-controller {
394 compatible = "riscv,cpu-intc";
395 interrupt-controller;
396 #interrupt-cells = <1>;
403 i-cache-block-size = <64>;
404 i-cache-size = <65536>;
405 i-cache-sets = <512>;
406 d-cache-block-size = <64>;
407 d-cache-size = <65536>;
408 d-cache-sets = <512>;
410 mmu-type = "riscv,sv48";
411 next-level-cache = <&l2_cache2>;
413 riscv,isa-base = "rv64i";
414 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
425 riscv,cbom-block-size = <64>;
426 riscv,cboz-block-size = <64>;
428 cpu11_intc: interrupt-controller {
429 compatible = "riscv,cpu-intc";
430 interrupt-controller;
431 #interrupt-cells = <1>;
438 i-cache-block-size = <64>;
439 i-cache-size = <65536>;
440 i-cache-sets = <512>;
441 d-cache-block-size = <64>;
442 d-cache-size = <65536>;
443 d-cache-sets = <512>;
445 mmu-type = "riscv,sv48";
446 next-level-cache = <&l2_cache3>;
448 riscv,isa-base = "rv64i";
449 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
460 riscv,cbom-block-size = <64>;
461 riscv,cboz-block-size = <64>;
463 cpu12_intc: interrupt-controller {
464 compatible = "riscv,cpu-intc";
465 interrupt-controller;
466 #interrupt-cells = <1>;
473 i-cache-block-size = <64>;
474 i-cache-size = <65536>;
475 i-cache-sets = <512>;
476 d-cache-block-size = <64>;
477 d-cache-size = <65536>;
478 d-cache-sets = <512>;
480 mmu-type = "riscv,sv48";
481 next-level-cache = <&l2_cache3>;
483 riscv,isa-base = "rv64i";
484 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
495 riscv,cbom-block-size = <64>;
496 riscv,cboz-block-size = <64>;
498 cpu13_intc: interrupt-controller {
499 compatible = "riscv,cpu-intc";
500 interrupt-controller;
501 #interrupt-cells = <1>;
508 i-cache-block-size = <64>;
509 i-cache-size = <65536>;
510 i-cache-sets = <512>;
511 d-cache-block-size = <64>;
512 d-cache-size = <65536>;
513 d-cache-sets = <512>;
515 mmu-type = "riscv,sv48";
516 next-level-cache = <&l2_cache3>;
518 riscv,isa-base = "rv64i";
519 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
530 riscv,cbom-block-size = <64>;
531 riscv,cboz-block-size = <64>;
533 cpu14_intc: interrupt-controller {
534 compatible = "riscv,cpu-intc";
535 interrupt-controller;
536 #interrupt-cells = <1>;
543 i-cache-block-size = <64>;
544 i-cache-size = <65536>;
545 i-cache-sets = <512>;
546 d-cache-block-size = <64>;
547 d-cache-size = <65536>;
548 d-cache-sets = <512>;
550 mmu-type = "riscv,sv48";
551 next-level-cache = <&l2_cache3>;
553 riscv,isa-base = "rv64i";
554 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
565 riscv,cbom-block-size = <64>;
566 riscv,cboz-block-size = <64>;
568 cpu15_intc: interrupt-controller {
569 compatible = "riscv,cpu-intc";
570 interrupt-controller;
571 #interrupt-cells = <1>;
578 i-cache-block-size = <64>;
579 i-cache-size = <65536>;
580 i-cache-sets = <512>;
581 d-cache-block-size = <64>;
582 d-cache-size = <65536>;
583 d-cache-sets = <512>;
585 mmu-type = "riscv,sv48";
586 next-level-cache = <&l2_cache4>;
588 riscv,isa-base = "rv64i";
589 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
600 riscv,cbom-block-size = <64>;
601 riscv,cboz-block-size = <64>;
603 cpu16_intc: interrupt-controller {
604 compatible = "riscv,cpu-intc";
605 interrupt-controller;
606 #interrupt-cells = <1>;
613 i-cache-block-size = <64>;
614 i-cache-size = <65536>;
615 i-cache-sets = <512>;
616 d-cache-block-size = <64>;
617 d-cache-size = <65536>;
618 d-cache-sets = <512>;
620 mmu-type = "riscv,sv48";
621 next-level-cache = <&l2_cache4>;
623 riscv,isa-base = "rv64i";
624 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
635 riscv,cbom-block-size = <64>;
636 riscv,cboz-block-size = <64>;
638 cpu17_intc: interrupt-controller {
639 compatible = "riscv,cpu-intc";
640 interrupt-controller;
641 #interrupt-cells = <1>;
648 i-cache-block-size = <64>;
649 i-cache-size = <65536>;
650 i-cache-sets = <512>;
651 d-cache-block-size = <64>;
652 d-cache-size = <65536>;
653 d-cache-sets = <512>;
655 mmu-type = "riscv,sv48";
656 next-level-cache = <&l2_cache4>;
658 riscv,isa-base = "rv64i";
659 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
670 riscv,cbom-block-size = <64>;
671 riscv,cboz-block-size = <64>;
673 cpu18_intc: interrupt-controller {
674 compatible = "riscv,cpu-intc";
675 interrupt-controller;
676 #interrupt-cells = <1>;
683 i-cache-block-size = <64>;
684 i-cache-size = <65536>;
685 i-cache-sets = <512>;
686 d-cache-block-size = <64>;
687 d-cache-size = <65536>;
688 d-cache-sets = <512>;
690 mmu-type = "riscv,sv48";
691 next-level-cache = <&l2_cache4>;
693 riscv,isa-base = "rv64i";
694 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
705 riscv,cbom-block-size = <64>;
706 riscv,cboz-block-size = <64>;
708 cpu19_intc: interrupt-controller {
709 compatible = "riscv,cpu-intc";
710 interrupt-controller;
711 #interrupt-cells = <1>;
718 i-cache-block-size = <64>;
719 i-cache-size = <65536>;
720 i-cache-sets = <512>;
721 d-cache-block-size = <64>;
722 d-cache-size = <65536>;
723 d-cache-sets = <512>;
725 mmu-type = "riscv,sv48";
726 next-level-cache = <&l2_cache5>;
728 riscv,isa-base = "rv64i";
729 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
740 riscv,cbom-block-size = <64>;
741 riscv,cboz-block-size = <64>;
743 cpu20_intc: interrupt-controller {
744 compatible = "riscv,cpu-intc";
745 interrupt-controller;
746 #interrupt-cells = <1>;
753 i-cache-block-size = <64>;
754 i-cache-size = <65536>;
755 i-cache-sets = <512>;
756 d-cache-block-size = <64>;
757 d-cache-size = <65536>;
758 d-cache-sets = <512>;
760 mmu-type = "riscv,sv48";
761 next-level-cache = <&l2_cache5>;
763 riscv,isa-base = "rv64i";
764 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
775 riscv,cbom-block-size = <64>;
776 riscv,cboz-block-size = <64>;
778 cpu21_intc: interrupt-controller {
779 compatible = "riscv,cpu-intc";
780 interrupt-controller;
781 #interrupt-cells = <1>;
788 i-cache-block-size = <64>;
789 i-cache-size = <65536>;
790 i-cache-sets = <512>;
791 d-cache-block-size = <64>;
792 d-cache-size = <65536>;
793 d-cache-sets = <512>;
795 mmu-type = "riscv,sv48";
796 next-level-cache = <&l2_cache5>;
798 riscv,isa-base = "rv64i";
799 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
810 riscv,cbom-block-size = <64>;
811 riscv,cboz-block-size = <64>;
813 cpu22_intc: interrupt-controller {
814 compatible = "riscv,cpu-intc";
815 interrupt-controller;
816 #interrupt-cells = <1>;
823 i-cache-block-size = <64>;
824 i-cache-size = <65536>;
825 i-cache-sets = <512>;
826 d-cache-block-size = <64>;
827 d-cache-size = <65536>;
828 d-cache-sets = <512>;
830 mmu-type = "riscv,sv48";
831 next-level-cache = <&l2_cache5>;
833 riscv,isa-base = "rv64i";
834 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
845 riscv,cbom-block-size = <64>;
846 riscv,cboz-block-size = <64>;
848 cpu23_intc: interrupt-controller {
849 compatible = "riscv,cpu-intc";
850 interrupt-controller;
851 #interrupt-cells = <1>;
858 i-cache-block-size = <64>;
859 i-cache-size = <65536>;
860 i-cache-sets = <512>;
861 d-cache-block-size = <64>;
862 d-cache-size = <65536>;
863 d-cache-sets = <512>;
865 mmu-type = "riscv,sv48";
866 next-level-cache = <&l2_cache6>;
868 riscv,isa-base = "rv64i";
869 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
880 riscv,cbom-block-size = <64>;
881 riscv,cboz-block-size = <64>;
883 cpu24_intc: interrupt-controller {
884 compatible = "riscv,cpu-intc";
885 interrupt-controller;
886 #interrupt-cells = <1>;
893 i-cache-block-size = <64>;
894 i-cache-size = <65536>;
895 i-cache-sets = <512>;
896 d-cache-block-size = <64>;
897 d-cache-size = <65536>;
898 d-cache-sets = <512>;
900 mmu-type = "riscv,sv48";
901 next-level-cache = <&l2_cache6>;
903 riscv,isa-base = "rv64i";
904 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
915 riscv,cbom-block-size = <64>;
916 riscv,cboz-block-size = <64>;
918 cpu25_intc: interrupt-controller {
919 compatible = "riscv,cpu-intc";
920 interrupt-controller;
921 #interrupt-cells = <1>;
928 i-cache-block-size = <64>;
929 i-cache-size = <65536>;
930 i-cache-sets = <512>;
931 d-cache-block-size = <64>;
932 d-cache-size = <65536>;
933 d-cache-sets = <512>;
935 mmu-type = "riscv,sv48";
936 next-level-cache = <&l2_cache6>;
938 riscv,isa-base = "rv64i";
939 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
950 riscv,cbom-block-size = <64>;
951 riscv,cboz-block-size = <64>;
953 cpu26_intc: interrupt-controller {
954 compatible = "riscv,cpu-intc";
955 interrupt-controller;
956 #interrupt-cells = <1>;
963 i-cache-block-size = <64>;
964 i-cache-size = <65536>;
965 i-cache-sets = <512>;
966 d-cache-block-size = <64>;
967 d-cache-size = <65536>;
968 d-cache-sets = <512>;
970 mmu-type = "riscv,sv48";
971 next-level-cache = <&l2_cache6>;
973 riscv,isa-base = "rv64i";
974 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
985 riscv,cbom-block-size = <64>;
986 riscv,cboz-block-size = <64>;
988 cpu27_intc: interrupt-controller {
989 compatible = "riscv,cpu-intc";
990 interrupt-controller;
991 #interrupt-cells = <1>;
998 i-cache-block-size = <64>;
999 i-cache-size = <65536>;
1000 i-cache-sets = <512>;
1001 d-cache-block-size = <64>;
1002 d-cache-size = <65536>;
1003 d-cache-sets = <512>;
1005 mmu-type = "riscv,sv48";
1006 next-level-cache = <&l2_cache7>;
1008 riscv,isa-base = "rv64i";
1009 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1020 riscv,cbom-block-size = <64>;
1021 riscv,cboz-block-size = <64>;
1023 cpu28_intc: interrupt-controller {
1024 compatible = "riscv,cpu-intc";
1025 interrupt-controller;
1026 #interrupt-cells = <1>;
1033 i-cache-block-size = <64>;
1034 i-cache-size = <65536>;
1035 i-cache-sets = <512>;
1036 d-cache-block-size = <64>;
1037 d-cache-size = <65536>;
1038 d-cache-sets = <512>;
1040 mmu-type = "riscv,sv48";
1041 next-level-cache = <&l2_cache7>;
1043 riscv,isa-base = "rv64i";
1044 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1055 riscv,cbom-block-size = <64>;
1056 riscv,cboz-block-size = <64>;
1058 cpu29_intc: interrupt-controller {
1059 compatible = "riscv,cpu-intc";
1060 interrupt-controller;
1061 #interrupt-cells = <1>;
1068 i-cache-block-size = <64>;
1069 i-cache-size = <65536>;
1070 i-cache-sets = <512>;
1071 d-cache-block-size = <64>;
1072 d-cache-size = <65536>;
1073 d-cache-sets = <512>;
1075 mmu-type = "riscv,sv48";
1076 next-level-cache = <&l2_cache7>;
1078 riscv,isa-base = "rv64i";
1079 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1090 riscv,cbom-block-size = <64>;
1091 riscv,cboz-block-size = <64>;
1093 cpu30_intc: interrupt-controller {
1094 compatible = "riscv,cpu-intc";
1095 interrupt-controller;
1096 #interrupt-cells = <1>;
1103 i-cache-block-size = <64>;
1104 i-cache-size = <65536>;
1105 i-cache-sets = <512>;
1106 d-cache-block-size = <64>;
1107 d-cache-size = <65536>;
1108 d-cache-sets = <512>;
1110 mmu-type = "riscv,sv48";
1111 next-level-cache = <&l2_cache7>;
1113 riscv,isa-base = "rv64i";
1114 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1125 riscv,cbom-block-size = <64>;
1126 riscv,cboz-block-size = <64>;
1128 cpu31_intc: interrupt-controller {
1129 compatible = "riscv,cpu-intc";
1130 interrupt-controller;
1131 #interrupt-cells = <1>;
1138 i-cache-block-size = <64>;
1139 i-cache-size = <65536>;
1140 i-cache-sets = <512>;
1141 d-cache-block-size = <64>;
1142 d-cache-size = <65536>;
1143 d-cache-sets = <512>;
1145 mmu-type = "riscv,sv48";
1146 next-level-cache = <&l2_cache8>;
1148 riscv,isa-base = "rv64i";
1149 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1160 riscv,cbom-block-size = <64>;
1161 riscv,cboz-block-size = <64>;
1163 cpu32_intc: interrupt-controller {
1164 compatible = "riscv,cpu-intc";
1165 interrupt-controller;
1166 #interrupt-cells = <1>;
1173 i-cache-block-size = <64>;
1174 i-cache-size = <65536>;
1175 i-cache-sets = <512>;
1176 d-cache-block-size = <64>;
1177 d-cache-size = <65536>;
1178 d-cache-sets = <512>;
1180 mmu-type = "riscv,sv48";
1181 next-level-cache = <&l2_cache8>;
1183 riscv,isa-base = "rv64i";
1184 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1195 riscv,cbom-block-size = <64>;
1196 riscv,cboz-block-size = <64>;
1198 cpu33_intc: interrupt-controller {
1199 compatible = "riscv,cpu-intc";
1200 interrupt-controller;
1201 #interrupt-cells = <1>;
1208 i-cache-block-size = <64>;
1209 i-cache-size = <65536>;
1210 i-cache-sets = <512>;
1211 d-cache-block-size = <64>;
1212 d-cache-size = <65536>;
1213 d-cache-sets = <512>;
1215 mmu-type = "riscv,sv48";
1216 next-level-cache = <&l2_cache8>;
1218 riscv,isa-base = "rv64i";
1219 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1230 riscv,cbom-block-size = <64>;
1231 riscv,cboz-block-size = <64>;
1233 cpu34_intc: interrupt-controller {
1234 compatible = "riscv,cpu-intc";
1235 interrupt-controller;
1236 #interrupt-cells = <1>;
1243 i-cache-block-size = <64>;
1244 i-cache-size = <65536>;
1245 i-cache-sets = <512>;
1246 d-cache-block-size = <64>;
1247 d-cache-size = <65536>;
1248 d-cache-sets = <512>;
1250 mmu-type = "riscv,sv48";
1251 next-level-cache = <&l2_cache8>;
1253 riscv,isa-base = "rv64i";
1254 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1265 riscv,cbom-block-size = <64>;
1266 riscv,cboz-block-size = <64>;
1268 cpu35_intc: interrupt-controller {
1269 compatible = "riscv,cpu-intc";
1270 interrupt-controller;
1271 #interrupt-cells = <1>;
1278 i-cache-block-size = <64>;
1279 i-cache-size = <65536>;
1280 i-cache-sets = <512>;
1281 d-cache-block-size = <64>;
1282 d-cache-size = <65536>;
1283 d-cache-sets = <512>;
1285 mmu-type = "riscv,sv48";
1286 next-level-cache = <&l2_cache9>;
1288 riscv,isa-base = "rv64i";
1289 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1300 riscv,cbom-block-size = <64>;
1301 riscv,cboz-block-size = <64>;
1303 cpu36_intc: interrupt-controller {
1304 compatible = "riscv,cpu-intc";
1305 interrupt-controller;
1306 #interrupt-cells = <1>;
1313 i-cache-block-size = <64>;
1314 i-cache-size = <65536>;
1315 i-cache-sets = <512>;
1316 d-cache-block-size = <64>;
1317 d-cache-size = <65536>;
1318 d-cache-sets = <512>;
1320 mmu-type = "riscv,sv48";
1321 next-level-cache = <&l2_cache9>;
1323 riscv,isa-base = "rv64i";
1324 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1335 riscv,cbom-block-size = <64>;
1336 riscv,cboz-block-size = <64>;
1338 cpu37_intc: interrupt-controller {
1339 compatible = "riscv,cpu-intc";
1340 interrupt-controller;
1341 #interrupt-cells = <1>;
1348 i-cache-block-size = <64>;
1349 i-cache-size = <65536>;
1350 i-cache-sets = <512>;
1351 d-cache-block-size = <64>;
1352 d-cache-size = <65536>;
1353 d-cache-sets = <512>;
1355 mmu-type = "riscv,sv48";
1356 next-level-cache = <&l2_cache9>;
1358 riscv,isa-base = "rv64i";
1359 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1370 riscv,cbom-block-size = <64>;
1371 riscv,cboz-block-size = <64>;
1373 cpu38_intc: interrupt-controller {
1374 compatible = "riscv,cpu-intc";
1375 interrupt-controller;
1376 #interrupt-cells = <1>;
1383 i-cache-block-size = <64>;
1384 i-cache-size = <65536>;
1385 i-cache-sets = <512>;
1386 d-cache-block-size = <64>;
1387 d-cache-size = <65536>;
1388 d-cache-sets = <512>;
1390 mmu-type = "riscv,sv48";
1391 next-level-cache = <&l2_cache9>;
1393 riscv,isa-base = "rv64i";
1394 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1405 riscv,cbom-block-size = <64>;
1406 riscv,cboz-block-size = <64>;
1408 cpu39_intc: interrupt-controller {
1409 compatible = "riscv,cpu-intc";
1410 interrupt-controller;
1411 #interrupt-cells = <1>;
1418 i-cache-block-size = <64>;
1419 i-cache-size = <65536>;
1420 i-cache-sets = <512>;
1421 d-cache-block-size = <64>;
1422 d-cache-size = <65536>;
1423 d-cache-sets = <512>;
1425 mmu-type = "riscv,sv48";
1426 next-level-cache = <&l2_cache10>;
1428 riscv,isa-base = "rv64i";
1429 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1440 riscv,cbom-block-size = <64>;
1441 riscv,cboz-block-size = <64>;
1443 cpu40_intc: interrupt-controller {
1444 compatible = "riscv,cpu-intc";
1445 interrupt-controller;
1446 #interrupt-cells = <1>;
1453 i-cache-block-size = <64>;
1454 i-cache-size = <65536>;
1455 i-cache-sets = <512>;
1456 d-cache-block-size = <64>;
1457 d-cache-size = <65536>;
1458 d-cache-sets = <512>;
1460 mmu-type = "riscv,sv48";
1461 next-level-cache = <&l2_cache10>;
1463 riscv,isa-base = "rv64i";
1464 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1475 riscv,cbom-block-size = <64>;
1476 riscv,cboz-block-size = <64>;
1478 cpu41_intc: interrupt-controller {
1479 compatible = "riscv,cpu-intc";
1480 interrupt-controller;
1481 #interrupt-cells = <1>;
1488 i-cache-block-size = <64>;
1489 i-cache-size = <65536>;
1490 i-cache-sets = <512>;
1491 d-cache-block-size = <64>;
1492 d-cache-size = <65536>;
1493 d-cache-sets = <512>;
1495 mmu-type = "riscv,sv48";
1496 next-level-cache = <&l2_cache10>;
1498 riscv,isa-base = "rv64i";
1499 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1510 riscv,cbom-block-size = <64>;
1511 riscv,cboz-block-size = <64>;
1513 cpu42_intc: interrupt-controller {
1514 compatible = "riscv,cpu-intc";
1515 interrupt-controller;
1516 #interrupt-cells = <1>;
1523 i-cache-block-size = <64>;
1524 i-cache-size = <65536>;
1525 i-cache-sets = <512>;
1526 d-cache-block-size = <64>;
1527 d-cache-size = <65536>;
1528 d-cache-sets = <512>;
1530 mmu-type = "riscv,sv48";
1531 next-level-cache = <&l2_cache10>;
1533 riscv,isa-base = "rv64i";
1534 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1545 riscv,cbom-block-size = <64>;
1546 riscv,cboz-block-size = <64>;
1548 cpu43_intc: interrupt-controller {
1549 compatible = "riscv,cpu-intc";
1550 interrupt-controller;
1551 #interrupt-cells = <1>;
1558 i-cache-block-size = <64>;
1559 i-cache-size = <65536>;
1560 i-cache-sets = <512>;
1561 d-cache-block-size = <64>;
1562 d-cache-size = <65536>;
1563 d-cache-sets = <512>;
1565 mmu-type = "riscv,sv48";
1566 next-level-cache = <&l2_cache11>;
1568 riscv,isa-base = "rv64i";
1569 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1580 riscv,cbom-block-size = <64>;
1581 riscv,cboz-block-size = <64>;
1583 cpu44_intc: interrupt-controller {
1584 compatible = "riscv,cpu-intc";
1585 interrupt-controller;
1586 #interrupt-cells = <1>;
1593 i-cache-block-size = <64>;
1594 i-cache-size = <65536>;
1595 i-cache-sets = <512>;
1596 d-cache-block-size = <64>;
1597 d-cache-size = <65536>;
1598 d-cache-sets = <512>;
1600 mmu-type = "riscv,sv48";
1601 next-level-cache = <&l2_cache11>;
1603 riscv,isa-base = "rv64i";
1604 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1615 riscv,cbom-block-size = <64>;
1616 riscv,cboz-block-size = <64>;
1618 cpu45_intc: interrupt-controller {
1619 compatible = "riscv,cpu-intc";
1620 interrupt-controller;
1621 #interrupt-cells = <1>;
1628 i-cache-block-size = <64>;
1629 i-cache-size = <65536>;
1630 i-cache-sets = <512>;
1631 d-cache-block-size = <64>;
1632 d-cache-size = <65536>;
1633 d-cache-sets = <512>;
1635 mmu-type = "riscv,sv48";
1636 next-level-cache = <&l2_cache11>;
1638 riscv,isa-base = "rv64i";
1639 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1650 riscv,cbom-block-size = <64>;
1651 riscv,cboz-block-size = <64>;
1653 cpu46_intc: interrupt-controller {
1654 compatible = "riscv,cpu-intc";
1655 interrupt-controller;
1656 #interrupt-cells = <1>;
1663 i-cache-block-size = <64>;
1664 i-cache-size = <65536>;
1665 i-cache-sets = <512>;
1666 d-cache-block-size = <64>;
1667 d-cache-size = <65536>;
1668 d-cache-sets = <512>;
1670 mmu-type = "riscv,sv48";
1671 next-level-cache = <&l2_cache11>;
1673 riscv,isa-base = "rv64i";
1674 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1685 riscv,cbom-block-size = <64>;
1686 riscv,cboz-block-size = <64>;
1688 cpu47_intc: interrupt-controller {
1689 compatible = "riscv,cpu-intc";
1690 interrupt-controller;
1691 #interrupt-cells = <1>;
1698 i-cache-block-size = <64>;
1699 i-cache-size = <65536>;
1700 i-cache-sets = <512>;
1701 d-cache-block-size = <64>;
1702 d-cache-size = <65536>;
1703 d-cache-sets = <512>;
1705 mmu-type = "riscv,sv48";
1706 next-level-cache = <&l2_cache12>;
1708 riscv,isa-base = "rv64i";
1709 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1720 riscv,cbom-block-size = <64>;
1721 riscv,cboz-block-size = <64>;
1723 cpu48_intc: interrupt-controller {
1724 compatible = "riscv,cpu-intc";
1725 interrupt-controller;
1726 #interrupt-cells = <1>;
1733 i-cache-block-size = <64>;
1734 i-cache-size = <65536>;
1735 i-cache-sets = <512>;
1736 d-cache-block-size = <64>;
1737 d-cache-size = <65536>;
1738 d-cache-sets = <512>;
1740 mmu-type = "riscv,sv48";
1741 next-level-cache = <&l2_cache12>;
1743 riscv,isa-base = "rv64i";
1744 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1755 riscv,cbom-block-size = <64>;
1756 riscv,cboz-block-size = <64>;
1758 cpu49_intc: interrupt-controller {
1759 compatible = "riscv,cpu-intc";
1760 interrupt-controller;
1761 #interrupt-cells = <1>;
1768 i-cache-block-size = <64>;
1769 i-cache-size = <65536>;
1770 i-cache-sets = <512>;
1771 d-cache-block-size = <64>;
1772 d-cache-size = <65536>;
1773 d-cache-sets = <512>;
1775 mmu-type = "riscv,sv48";
1776 next-level-cache = <&l2_cache12>;
1778 riscv,isa-base = "rv64i";
1779 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1790 riscv,cbom-block-size = <64>;
1791 riscv,cboz-block-size = <64>;
1793 cpu50_intc: interrupt-controller {
1794 compatible = "riscv,cpu-intc";
1795 interrupt-controller;
1796 #interrupt-cells = <1>;
1803 i-cache-block-size = <64>;
1804 i-cache-size = <65536>;
1805 i-cache-sets = <512>;
1806 d-cache-block-size = <64>;
1807 d-cache-size = <65536>;
1808 d-cache-sets = <512>;
1810 mmu-type = "riscv,sv48";
1811 next-level-cache = <&l2_cache12>;
1813 riscv,isa-base = "rv64i";
1814 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1825 riscv,cbom-block-size = <64>;
1826 riscv,cboz-block-size = <64>;
1828 cpu51_intc: interrupt-controller {
1829 compatible = "riscv,cpu-intc";
1830 interrupt-controller;
1831 #interrupt-cells = <1>;
1838 i-cache-block-size = <64>;
1839 i-cache-size = <65536>;
1840 i-cache-sets = <512>;
1841 d-cache-block-size = <64>;
1842 d-cache-size = <65536>;
1843 d-cache-sets = <512>;
1845 mmu-type = "riscv,sv48";
1846 next-level-cache = <&l2_cache13>;
1848 riscv,isa-base = "rv64i";
1849 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1860 riscv,cbom-block-size = <64>;
1861 riscv,cboz-block-size = <64>;
1863 cpu52_intc: interrupt-controller {
1864 compatible = "riscv,cpu-intc";
1865 interrupt-controller;
1866 #interrupt-cells = <1>;
1873 i-cache-block-size = <64>;
1874 i-cache-size = <65536>;
1875 i-cache-sets = <512>;
1876 d-cache-block-size = <64>;
1877 d-cache-size = <65536>;
1878 d-cache-sets = <512>;
1880 mmu-type = "riscv,sv48";
1881 next-level-cache = <&l2_cache13>;
1883 riscv,isa-base = "rv64i";
1884 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1895 riscv,cbom-block-size = <64>;
1896 riscv,cboz-block-size = <64>;
1898 cpu53_intc: interrupt-controller {
1899 compatible = "riscv,cpu-intc";
1900 interrupt-controller;
1901 #interrupt-cells = <1>;
1908 i-cache-block-size = <64>;
1909 i-cache-size = <65536>;
1910 i-cache-sets = <512>;
1911 d-cache-block-size = <64>;
1912 d-cache-size = <65536>;
1913 d-cache-sets = <512>;
1915 mmu-type = "riscv,sv48";
1916 next-level-cache = <&l2_cache13>;
1918 riscv,isa-base = "rv64i";
1919 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1930 riscv,cbom-block-size = <64>;
1931 riscv,cboz-block-size = <64>;
1933 cpu54_intc: interrupt-controller {
1934 compatible = "riscv,cpu-intc";
1935 interrupt-controller;
1936 #interrupt-cells = <1>;
1943 i-cache-block-size = <64>;
1944 i-cache-size = <65536>;
1945 i-cache-sets = <512>;
1946 d-cache-block-size = <64>;
1947 d-cache-size = <65536>;
1948 d-cache-sets = <512>;
1950 mmu-type = "riscv,sv48";
1951 next-level-cache = <&l2_cache13>;
1953 riscv,isa-base = "rv64i";
1954 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1965 riscv,cbom-block-size = <64>;
1966 riscv,cboz-block-size = <64>;
1968 cpu55_intc: interrupt-controller {
1969 compatible = "riscv,cpu-intc";
1970 interrupt-controller;
1971 #interrupt-cells = <1>;
1978 i-cache-block-size = <64>;
1979 i-cache-size = <65536>;
1980 i-cache-sets = <512>;
1981 d-cache-block-size = <64>;
1982 d-cache-size = <65536>;
1983 d-cache-sets = <512>;
1985 mmu-type = "riscv,sv48";
1986 next-level-cache = <&l2_cache14>;
1988 riscv,isa-base = "rv64i";
1989 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2000 riscv,cbom-block-size = <64>;
2001 riscv,cboz-block-size = <64>;
2003 cpu56_intc: interrupt-controller {
2004 compatible = "riscv,cpu-intc";
2005 interrupt-controller;
2006 #interrupt-cells = <1>;
2013 i-cache-block-size = <64>;
2014 i-cache-size = <65536>;
2015 i-cache-sets = <512>;
2016 d-cache-block-size = <64>;
2017 d-cache-size = <65536>;
2018 d-cache-sets = <512>;
2020 mmu-type = "riscv,sv48";
2021 next-level-cache = <&l2_cache14>;
2023 riscv,isa-base = "rv64i";
2024 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2035 riscv,cbom-block-size = <64>;
2036 riscv,cboz-block-size = <64>;
2038 cpu57_intc: interrupt-controller {
2039 compatible = "riscv,cpu-intc";
2040 interrupt-controller;
2041 #interrupt-cells = <1>;
2048 i-cache-block-size = <64>;
2049 i-cache-size = <65536>;
2050 i-cache-sets = <512>;
2051 d-cache-block-size = <64>;
2052 d-cache-size = <65536>;
2053 d-cache-sets = <512>;
2055 mmu-type = "riscv,sv48";
2056 next-level-cache = <&l2_cache14>;
2058 riscv,isa-base = "rv64i";
2059 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2070 riscv,cbom-block-size = <64>;
2071 riscv,cboz-block-size = <64>;
2073 cpu58_intc: interrupt-controller {
2074 compatible = "riscv,cpu-intc";
2075 interrupt-controller;
2076 #interrupt-cells = <1>;
2083 i-cache-block-size = <64>;
2084 i-cache-size = <65536>;
2085 i-cache-sets = <512>;
2086 d-cache-block-size = <64>;
2087 d-cache-size = <65536>;
2088 d-cache-sets = <512>;
2090 mmu-type = "riscv,sv48";
2091 next-level-cache = <&l2_cache14>;
2093 riscv,isa-base = "rv64i";
2094 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2105 riscv,cbom-block-size = <64>;
2106 riscv,cboz-block-size = <64>;
2108 cpu59_intc: interrupt-controller {
2109 compatible = "riscv,cpu-intc";
2110 interrupt-controller;
2111 #interrupt-cells = <1>;
2118 i-cache-block-size = <64>;
2119 i-cache-size = <65536>;
2120 i-cache-sets = <512>;
2121 d-cache-block-size = <64>;
2122 d-cache-size = <65536>;
2123 d-cache-sets = <512>;
2125 mmu-type = "riscv,sv48";
2126 next-level-cache = <&l2_cache15>;
2128 riscv,isa-base = "rv64i";
2129 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2140 riscv,cbom-block-size = <64>;
2141 riscv,cboz-block-size = <64>;
2143 cpu60_intc: interrupt-controller {
2144 compatible = "riscv,cpu-intc";
2145 interrupt-controller;
2146 #interrupt-cells = <1>;
2153 i-cache-block-size = <64>;
2154 i-cache-size = <65536>;
2155 i-cache-sets = <512>;
2156 d-cache-block-size = <64>;
2157 d-cache-size = <65536>;
2158 d-cache-sets = <512>;
2160 mmu-type = "riscv,sv48";
2161 next-level-cache = <&l2_cache15>;
2163 riscv,isa-base = "rv64i";
2164 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2175 riscv,cbom-block-size = <64>;
2176 riscv,cboz-block-size = <64>;
2178 cpu61_intc: interrupt-controller {
2179 compatible = "riscv,cpu-intc";
2180 interrupt-controller;
2181 #interrupt-cells = <1>;
2188 i-cache-block-size = <64>;
2189 i-cache-size = <65536>;
2190 i-cache-sets = <512>;
2191 d-cache-block-size = <64>;
2192 d-cache-size = <65536>;
2193 d-cache-sets = <512>;
2195 mmu-type = "riscv,sv48";
2196 next-level-cache = <&l2_cache15>;
2198 riscv,isa-base = "rv64i";
2199 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2210 riscv,cbom-block-size = <64>;
2211 riscv,cboz-block-size = <64>;
2213 cpu62_intc: interrupt-controller {
2214 compatible = "riscv,cpu-intc";
2215 interrupt-controller;
2216 #interrupt-cells = <1>;
2223 i-cache-block-size = <64>;
2224 i-cache-size = <65536>;
2225 i-cache-sets = <512>;
2226 d-cache-block-size = <64>;
2227 d-cache-size = <65536>;
2228 d-cache-sets = <512>;
2230 mmu-type = "riscv,sv48";
2231 next-level-cache = <&l2_cache15>;
2233 riscv,isa-base = "rv64i";
2234 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2245 riscv,cbom-block-size = <64>;
2246 riscv,cboz-block-size = <64>;
2248 cpu63_intc: interrupt-controller {
2249 compatible = "riscv,cpu-intc";
2250 interrupt-controller;
2251 #interrupt-cells = <1>;
2255 cpu-map {
2547 l2_cache0: cache-controller-0 {
2548 compatible = "cache";
2549 cache-block-size = <64>;
2550 cache-level = <2>;
2551 cache-size = <2097152>;
2552 cache-sets = <2048>;
2553 cache-unified;
2554 next-level-cache = <&l3_cache>;
2557 l2_cache1: cache-controller-1 {
2558 compatible = "cache";
2559 cache-block-size = <64>;
2560 cache-level = <2>;
2561 cache-size = <2097152>;
2562 cache-sets = <2048>;
2563 cache-unified;
2564 next-level-cache = <&l3_cache>;
2567 l2_cache2: cache-controller-2 {
2568 compatible = "cache";
2569 cache-block-size = <64>;
2570 cache-level = <2>;
2571 cache-size = <2097152>;
2572 cache-sets = <2048>;
2573 cache-unified;
2574 next-level-cache = <&l3_cache>;
2577 l2_cache3: cache-controller-3 {
2578 compatible = "cache";
2579 cache-block-size = <64>;
2580 cache-level = <2>;
2581 cache-size = <2097152>;
2582 cache-sets = <2048>;
2583 cache-unified;
2584 next-level-cache = <&l3_cache>;
2587 l2_cache4: cache-controller-4 {
2588 compatible = "cache";
2589 cache-block-size = <64>;
2590 cache-level = <2>;
2591 cache-size = <2097152>;
2592 cache-sets = <2048>;
2593 cache-unified;
2594 next-level-cache = <&l3_cache>;
2597 l2_cache5: cache-controller-5 {
2598 compatible = "cache";
2599 cache-block-size = <64>;
2600 cache-level = <2>;
2601 cache-size = <2097152>;
2602 cache-sets = <2048>;
2603 cache-unified;
2604 next-level-cache = <&l3_cache>;
2607 l2_cache6: cache-controller-6 {
2608 compatible = "cache";
2609 cache-block-size = <64>;
2610 cache-level = <2>;
2611 cache-size = <2097152>;
2612 cache-sets = <2048>;
2613 cache-unified;
2614 next-level-cache = <&l3_cache>;
2617 l2_cache7: cache-controller-7 {
2618 compatible = "cache";
2619 cache-block-size = <64>;
2620 cache-level = <2>;
2621 cache-size = <2097152>;
2622 cache-sets = <2048>;
2623 cache-unified;
2624 next-level-cache = <&l3_cache>;
2627 l2_cache8: cache-controller-8 {
2628 compatible = "cache";
2629 cache-block-size = <64>;
2630 cache-level = <2>;
2631 cache-size = <2097152>;
2632 cache-sets = <2048>;
2633 cache-unified;
2634 next-level-cache = <&l3_cache>;
2637 l2_cache9: cache-controller-9 {
2638 compatible = "cache";
2639 cache-block-size = <64>;
2640 cache-level = <2>;
2641 cache-size = <2097152>;
2642 cache-sets = <2048>;
2643 cache-unified;
2644 next-level-cache = <&l3_cache>;
2647 l2_cache10: cache-controller-10 {
2648 compatible = "cache";
2649 cache-block-size = <64>;
2650 cache-level = <2>;
2651 cache-size = <2097152>;
2652 cache-sets = <2048>;
2653 cache-unified;
2654 next-level-cache = <&l3_cache>;
2657 l2_cache11: cache-controller-11 {
2658 compatible = "cache";
2659 cache-block-size = <64>;
2660 cache-level = <2>;
2661 cache-size = <2097152>;
2662 cache-sets = <2048>;
2663 cache-unified;
2664 next-level-cache = <&l3_cache>;
2667 l2_cache12: cache-controller-12 {
2668 compatible = "cache";
2669 cache-block-size = <64>;
2670 cache-level = <2>;
2671 cache-size = <2097152>;
2672 cache-sets = <2048>;
2673 cache-unified;
2674 next-level-cache = <&l3_cache>;
2677 l2_cache13: cache-controller-13 {
2678 compatible = "cache";
2679 cache-block-size = <64>;
2680 cache-level = <2>;
2681 cache-size = <2097152>;
2682 cache-sets = <2048>;
2683 cache-unified;
2684 next-level-cache = <&l3_cache>;
2687 l2_cache14: cache-controller-14 {
2688 compatible = "cache";
2689 cache-block-size = <64>;
2690 cache-level = <2>;
2691 cache-size = <2097152>;
2692 cache-sets = <2048>;
2693 cache-unified;
2694 next-level-cache = <&l3_cache>;
2697 l2_cache15: cache-controller-15 {
2698 compatible = "cache";
2699 cache-block-size = <64>;
2700 cache-level = <2>;
2701 cache-size = <2097152>;
2702 cache-sets = <2048>;
2703 cache-unified;
2704 next-level-cache = <&l3_cache>;
2707 l3_cache: cache-controller-16 {
2708 compatible = "cache";
2709 cache-block-size = <64>;
2710 cache-level = <3>;
2711 cache-size = <67108864>;
2712 cache-sets = <4096>;
2713 cache-unified;
2718 intc: interrupt-controller@6d40000000 {
2719 compatible = "sophgo,sg2044-plic", "thead,c900-plic";
2720 #address-cells = <0>;
2721 #interrupt-cells = <2>;
2723 interrupt-controller;
2724 interrupts-extended =
2792 aclint_mswi: interrupt-controller@6d44000000 {
2793 compatible = "sophgo,sg2044-aclint-mswi", "thead,c900-aclint-mswi";
2795 interrupts-extended = <&cpu0_intc 3>,
2862 compatible = "sophgo,sg2044-aclint-mtimer", "thead,c900-aclint-mtimer";
2864 reg-names = "mtimecmp";
2865 interrupts-extended = <&cpu0_intc 7>,
2931 aclint_sswi: interrupt-controller@6d4400c000 {
2932 compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
2934 #interrupt-cells = <0>;
2935 interrupt-controller;
2936 interrupts-extended = <&cpu0_intc 1>,