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/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,etop-xway.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
14 pattern: "^ethernet@[0-9a-f]+$"
17 const: lantiq,etop-xway
24 - description: TX interrupt
25 - description: RX interrupt
27 interrupt-names:
[all …]
H A Dsamsung-sxgbe.txt4 - compatible: Should be "samsung,sxgbe-v2.0a"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the SXGBE interrupts
9 index 0 - this is fixed common interrupt of SXGBE and it is always
11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts
13 - phy-mode: String, operation mode of the PHY interface.
15 - samsung,pbl: Integer, Programmable Burst Length.
17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
18 This is an integer and represents allowable DMA bursts when fixed burst.
19 Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
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H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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H A Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
48 itc-setting:
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H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
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/linux/drivers/leds/
H A Dleds-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org>
5 * Partly based on drivers/leds/leds-turris-omnia.c, which is:
12 #include <linux/dma-mapping.h>
16 #include <linux/led-class-multicolor.h>
98 static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length) in sun50i_a100_ledc_dma_xfer() argument
103 desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle, in sun50i_a100_ledc_dma_xfer()
104 LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0); in sun50i_a100_ledc_dma_xfer()
106 return -ENOMEM; in sun50i_a100_ledc_dma_xfer()
110 return -EIO; in sun50i_a100_ledc_dma_xfer()
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/linux/drivers/video/fbdev/
H A Docfb.c12 #include <linux/dma-mapping.h>
36 #define OCFB_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
41 #define OCFB_CTRL_VBL1 0x00000000 /* Burst Length 1 */
42 #define OCFB_CTRL_VBL2 0x00000080 /* Burst Length 2 */
43 #define OCFB_CTRL_VBL4 0x00000100 /* Burst Length 4 */
44 #define OCFB_CTRL_VBL8 0x00000180 /* Burst Length 8 */
89 if (fbdev->little_endian) in ocfb_readreg()
90 return ioread32(fbdev->regs + offset); in ocfb_readreg()
92 return ioread32be(fbdev->regs + offset); in ocfb_readreg()
97 if (fbdev->little_endian) in ocfb_writereg()
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/linux/drivers/dma/
H A Didma64.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for the Intel integrated DMA 64-bit
16 #include <linux/io-64-nonatomic-lo-hi.h>
18 #include "virt-dma.h"
46 #define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */
48 #define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
49 #define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
54 #define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1)
59 #define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
60 #define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
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H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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/linux/Documentation/devicetree/bindings/dma/
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
[all …]
H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
41 * length according to the BLEN programmed (by default all BLEN are in dwmac1000_dma_axi()
[all …]
H A Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
97 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
185 /*--- DMA BLOCK defines ---*/
188 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
[all …]
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
32 * up of one or more DMA bursts. The DMA burst implementation mechanism is,
34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset
37 * writing threshold, SPICC starts a writing request burst, which reads the
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
77 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
105 u32 t_bacc; /* burst access valid clock to output delay */
131 #define GPMC_BURST_4 4 /* 4 word burst */
132 #define GPMC_BURST_8 8 /* 8 word burst */
133 #define GPMC_BURST_16 16 /* 16 word burst */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
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/linux/include/uapi/linux/netfilter/
H A Dxt_hashlimit.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 /* packet length accounting is done in 16-byte steps */
35 __u32 burst; /* Period multiplier for upper limit. */ member
59 __u32 burst; /* Period multiplier for upper limit. */ member
72 __u64 burst; /* Period multiplier for upper limit. */ member
86 __u64 burst; /* Period multiplier for upper limit. */ member
/linux/arch/mips/boot/dts/lantiq/
H A Ddanube_easy50712.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
19 #address-cells = <1>;
20 #size-cells = <1>;
22 #address-cells = <2>;
23 #size-cells = <1>;
26 compatible = "lantiq,localbus", "simple-bus";
28 nor-boot@0 {
30 bank-width = <2>;
32 #address-cells = <1>;
[all …]
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
53 * Lane LP-00 Line state immediately before the HS-0 Line
86 * Time, in picoseconds, that the transmitter drives the HS-0
88 * burst.
97 * Time, in picoseconds, that the transmitter drives the HS-0
116 * of @hs_trail or @clk_trail, to the start of the LP- 11
117 * state following a HS burst.
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/linux/sound/soc/sof/intel/
H A Dhda-pcm.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
22 #include "../sof-audio.h"
27 #define SDnFMT_MULT(x) (((x) - 1) << 11)
28 #define SDnFMT_DIV(x) (((x) - 1) << 8)
42 static int hda_force_pause_support = -1;
45 "Pause support: -1: Use default, 0: Disable, 1: Enable (default -1)");
75 dev_warn(sdev->dev, "can't find div rate %d using 48kHz\n", in hda_dsp_get_mult_div()
95 dev_warn(sdev->dev, "can't find %d bits using 16bit\n", in hda_dsp_get_bits()
106 struct hdac_stream *hstream = substream->runtime->private_data; in hda_dsp_pcm_hw_params()
108 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; in hda_dsp_pcm_hw_params()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
194 AHB32_AHB32, /* 2x AHB: 32-bit port 0 and 32-bit port 1 */
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
35 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
37 if (chip->ops->pci_address) in dw_edma_get_pci_address()
38 return chip->ops->pci_address(chip->dev, cpu_addr); in dw_edma_get_pci_address()
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