1 // SPDX-License-Identifier: GPL-2.0-only
19 	wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));  in wl1251_boot_target_enable_interrupts()
40 			/* 1.2 check pWhalBus->uSelfClearTime if the  in wl1251_boot_soft_reset()
43 			return -1;  in wl1251_boot_soft_reset()
118 	 * PG 1.2: set the clock request time to be ref_clk_settling_time -  in wl1251_boot_init_seq()
122 		tmp = init_data - 0x21;  in wl1251_boot_init_seq()
146 	/* set fractional divider according to Appendix C-BB PLL  in wl1251_boot_init_seq()
172 	 * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL  in wl1251_boot_init_seq()
173 	 * constant leakage current to linearize PFD to 0uA -  in wl1251_boot_init_seq()
181 	 * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],  in wl1251_boot_init_seq()
182 	 * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB  in wl1251_boot_init_seq()
183 	 * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]  in wl1251_boot_init_seq()
219 	if (chip_id != wl->chip_id) {  in wl1251_boot_run_firmware()
221 		return -EIO;  in wl1251_boot_run_firmware()
233 			return -EIO;  in wl1251_boot_run_firmware()
246 		return -EIO;  in wl1251_boot_run_firmware()
250 	wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);  in wl1251_boot_run_firmware()
253 	wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);  in wl1251_boot_run_firmware()
262 		     wl->cmd_box_addr, wl->event_box_addr);  in wl1251_boot_run_firmware()
264 	wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));  in wl1251_boot_run_firmware()
275 	wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |  in wl1251_boot_run_firmware()
283 	wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |  in wl1251_boot_run_firmware()
314 	/* 10.0 check firmware length and set partition */  in wl1251_boot_upload_firmware()
315 	fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |  in wl1251_boot_upload_firmware()
316 		(wl->fw[6] << 8) | (wl->fw[7]);  in wl1251_boot_upload_firmware()
322 		wl1251_error("firmware length not multiple of four");  in wl1251_boot_upload_firmware()
323 		return -EIO;  in wl1251_boot_upload_firmware()
329 		return -ENOMEM;  in wl1251_boot_upload_firmware()
359 		p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;  in wl1251_boot_upload_firmware()
373 	p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;  in wl1251_boot_upload_firmware()
395 	nvs = wl->nvs;  in wl1251_boot_upload_nvs()
397 		return -ENODEV;  in wl1251_boot_upload_nvs()
401 	nvs_len = wl->nvs_len;  in wl1251_boot_upload_nvs()
402 	nvs_start = wl->fw_len;  in wl1251_boot_upload_nvs()
406 	 * 1 byte : burst length.  in wl1251_boot_upload_nvs()
408 	 * n bytes: data to burst copy.  in wl1251_boot_upload_nvs()
410 	 * This is ended by a 0 length, then the NVS tables.  in wl1251_boot_upload_nvs()
425 				     "nvs burst write 0x%x: 0x%x",  in wl1251_boot_upload_nvs()
435 	 * We've reached the first zero length, the first NVS table  in wl1251_boot_upload_nvs()
439 	nvs_len -= nvs_ptr - nvs;  in wl1251_boot_upload_nvs()
480 	if (wl->use_eeprom) {  in wl1251_boot()
482 		/* Wait for EEPROM NVS burst read to complete */  in wl1251_boot()
490 		/* write firmware's last address (ie. it's length) to  in wl1251_boot()
492 		wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);  in wl1251_boot()
499 	wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;  in wl1251_boot()
500 	wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;  in wl1251_boot()
504 	wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;  in wl1251_boot()
509 		     wl->boot_attr.radio_type, wl->boot_attr.major,  in wl1251_boot()
510 		     wl->boot_attr.minor, minor_minor_e2_ver);  in wl1251_boot()
522 	 * pWhalBus->uBootData and start uploading firmware  in wl1251_boot()
526 		ret = -EIO;  in wl1251_boot()