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/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra234-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra234-nvdec
32 clock-names:
34 - const: nvdec
[all …]
/linux/drivers/gpu/drm/tegra/
H A Driscv.c1 // SPDX-License-Identifier: GPL-2.0-only
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors() local
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
51 READ_PROP("nvidia,bl-manifest-offset", &bl->manifest_offset); in tegra_drm_riscv_read_descriptors()
52 READ_PROP("nvidia,bl-code-offset", &bl->code_offset); in tegra_drm_riscv_read_descriptors()
53 READ_PROP("nvidia,bl-data-offset", &bl->data_offset); in tegra_drm_riscv_read_descriptors()
[all …]
/linux/arch/arm/lib/
H A Dbacktrace-clang.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/lib/backtrace-clang.S
39 * If the call instruction was a bl we can look at the callers branch
45 * Unfortunately due to the stack frame layout we can't dump r0 - r3, but these
52 * optionally saved caller registers (r4 - r10)
53 * optionally saved arguments (r0 - r3)
57 * Functions start with the following code sequence:
60 * stmfd sp!, {r0 - r3} (optional)
69 * The frame for c_backtrace has pointers to the code of dump_stack. This is
82 * show_stack. It points at the instruction directly after the bl dump_stack.
[all …]
H A Dbacktrace.S1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define offset r8 macro
29 stmfd sp!, {r4 - r9, lr} @ Save an extra register so we have a location...
34 tst r1, #0x10 @ 26 or 32-bit mode?
38 movne mask, #0 @ mask for 32-bit
40 1: stmfd sp!, {pc} @ calculate offset of PC stored
43 sub offset, r0, r1
47 * optionally saved caller registers (r4 - r10)
52 * optionally saved arguments (r0 - r3)
55 * Functions start with the following code sequence:
[all …]
/linux/arch/powerpc/kernel/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
28 #include <asm/head-64.h>
29 #include <asm/asm-offsets.h>
42 #include <asm/ppc-opcode.h>
43 #include <asm/feature-fixups.h>
45 #include <asm/exception-64s.h>
[all …]
H A Dhead_85xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2004 MontaVista Software, Inc.
40 #include <asm/asm-offsets.h>
43 #include <asm/feature-fixups.h>
46 /* As with the other PowerPC ports, it is expected that when code
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
[all …]
H A Dhead_booke.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Macros used for common Book-e exception handling
32 * Note that entries 0-3 are used for the prolog code, and the remaining
36 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
63 lwz r11, TASK_STACK - THREAD(r10); \
101 addi r2, r2, -THREAD
110 bl prepare_transfer_to_handler
139 lwz r1, TASK_STACK - THREAD(r10)
141 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE)
148 /* To handle the additional exception priority levels on Book-E
[all …]
H A Dhead_8xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Low-level exception handlers and MMU support
13 * This file contains low-level support and setup for PowerPC 8xx
30 #include <asm/asm-offsets.h>
32 #include <asm/code-patching-asm.h>
52 * support an ELF compressed (zImage) boot from EPPC-Bug because the
53 * code there loads up some registers before calling us:
56 * r5: initrd_end - unused if r4 is 0
61 * adding more processor specific branches around code I don't need.
[all …]
H A Dhead_book3s_32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Low-level exception handlers and MMU support
14 * This file contains the low-level support and setup for the
30 #include <asm/asm-offsets.h>
34 #include <asm/feature-fixups.h>
40 /* see the comment for clear_bats() -- Cort */ \
65 * -- Cort
77 * pointer (r1) points to just below the end of the half-meg region
78 * from 0x380000 - 0x400000, which is mapped in already.
[all …]
H A Dhead_44x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2005 MontaVista Software, Inc.
35 #include <asm/asm-offsets.h>
38 #include <asm/code-patching-asm.h>
42 /* As with the other PowerPC ports, it is expected that when code
46 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
[all …]
/linux/arch/arm64/kernel/
H A Dftrace.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <asm/debug-monitors.h>
18 #include <asm/text-patching.h>
23 int offset; member
29 .offset = offsetof(struct __arch_ftrace_regs, field), \
55 if (!strcmp(roff->name, name)) in ftrace_regs_query_register_offset()
56 return roff->offset; in ftrace_regs_query_register_offset()
59 return -EINVAL; in ftrace_regs_query_register_offset()
73 * When using patchable-function-entry without pre-function NOPS, addr in ftrace_call_adjust()
79 * addr+04: NOP // To be patched to BL <caller> in ftrace_call_adjust()
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/linux/fs/nfs/blocklayout/
H A Dblocklayout.c54 switch (be->be_state) { in is_hole()
58 return be->be_tag ? false : true; in is_hole()
79 rv->data = data; in alloc_parallel()
80 kref_init(&rv->refcnt); in alloc_parallel()
87 kref_get(&p->refcnt); in get_parallel()
95 p->pnfs_callback(p->data); in destroy_parallel()
101 kref_put(&p->refcnt, destroy_parallel); in put_parallel()
108 get_parallel(bio->bi_private); in bl_submit_bio()
111 bio->bi_iter.bi_size, in bl_submit_bio()
112 (unsigned long long)bio->bi_iter.bi_sector); in bl_submit_bio()
[all …]
/linux/arch/arm/boot/compressed/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
26 * Note that these macros must not contain any code which is not
82 bl putc
88 bl phex
101 kputc #'-'
105 kputc #'-'
[all …]
/linux/include/linux/
H A Dbio.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 bvec_iter_bvec((bio)->bi_io_vec, (iter))
27 bvec_iter_page((bio)->bi_io_vec, (iter))
29 bvec_iter_len((bio)->bi_io_vec, (iter))
31 bvec_iter_offset((bio)->bi_io_vec, (iter))
33 #define bio_page(bio) bio_iter_page((bio), (bio)->bi_iter)
34 #define bio_offset(bio) bio_iter_offset((bio), (bio)->bi_iter)
35 #define bio_iovec(bio) bio_iter_iovec((bio), (bio)->bi_iter)
40 #define bio_sectors(bio) bvec_iter_sectors((bio)->bi_iter)
41 #define bio_end_sector(bio) bvec_iter_end_sector((bio)->bi_iter)
[all …]
/linux/arch/loongarch/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
18 #include "efi-header.S"
23 .word IMAGE_DOS_SIGNATURE /* "MZ", MS-DOS header */
27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */
30 .long pe_header - _head /* Offset to the PE header */
60 la.pcrel t1, __bss_stop - LONGSIZE
85 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
91 bl relocate_kernel
95 PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
[all …]
/linux/arch/arm/kernel/
H A Dentry-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-common.S
14 #include <asm/unistd-oabi.h>
19 #include "entry-header.S"
37 * have tracing, context tracking and rseq debug disabled - the overheads
45 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
49 restore_user_regs fast = 1, offset = S_OFF
72 bl do_rseq_syscall
75 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
81 /* Slower path - fall through to work_pending */
[all …]
H A Dhead-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
68 * The following fragment of code is executed with the MMU on in MMU mode,
71 * r0 = cp#15 control register (exc_ret for M-class)
90 bl __inflate_kernel_data @ decompress .data to RAM
98 bl __memcpy @ copy .data to RAM
106 bl __memset @ clear .bss
118 bl kasan_early_init
[all …]
H A Dentry-header.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
29 * The SWI code relies on the fact that R0 is at the bottom of the stack
59 * ARMv7-M exception entry/exit macros.
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dlite5200_sleep.S1 /* SPDX-License-Identifier: GPL-2.0 */
41 /* ---------------------------------------------------------------------- */
42 /* low-power mode with help of M68HLC908QT1 */
50 /* setup wakeup address for u-boot at physical location 0x0 */
60 * 0xf0 (0xe0->0x100 gets overwritten when BDI connected;
62 * WARNING: self-refresh doesn't seem to work when BDI2000 is connected,
63 * possibly because BDI sets SDRAM registers before wakeup code does
72 bl save_regs
75 bl flush_data_cache
78 /* copy code to sram */
[all …]
/linux/arch/powerpc/crypto/
H A Daes-spe-modes.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include "aes-spe-regs.h"
14 lwz reg,off(rSP); /* load with offset */
16 stw reg,off(rDP); /* save with offset */
21 lwz reg,off(rIP); /* IV loading with offset */
23 stw reg,off(rIP); /* IV saving with offset */
81 stwu r1,-160(r1); /* create stack frame */ \
82 lis rT0,tab@h; /* en-/decryption table pointer */ \
116 stw r0,40(r1); /* the same code */ \
135 cmpwi d3,-1; \
[all …]
/linux/arch/arm/include/asm/
H A Dassembler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
10 * Do not include any C declarations in this file - it is included by
17 #error "Only include this from assembly code"
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
26 #include <asm/uaccess-asm.h>
57 /* Select code for any configuration running in BE8 mode */
59 #define ARM_BE8(code...) code argument
61 #define ARM_BE8(code...) argument
[all …]
/linux/drivers/target/
H A Dtarget_core_iblock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * This file contains the Storage Engine <-> Linux BlockIO transport
8 * (c) Copyright 2003-2013 Datera, Inc.
19 #include <linux/blk-integrity.h>
48 pr_debug("CORE_HBA[%d] - TCM iBlock HBA Driver %s on" in iblock_attach_hba()
49 " Generic Target Core Stack %s\n", hba->hba_id, in iblock_attach_hba()
67 ib_dev->ibd_exclusive = true; in iblock_alloc_device()
69 ib_dev->ibd_plug = kcalloc(nr_cpu_ids, sizeof(*ib_dev->ibd_plug), in iblock_alloc_device()
71 if (!ib_dev->ibd_plug) in iblock_alloc_device()
76 return &ib_dev->dev; in iblock_alloc_device()
[all …]
/linux/arch/sh/kernel/cpu/sh3/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2003 - 2012 Paul Mundt
11 #include <asm/asm-offsets.h>
23 * entry.S contains the system-call and fault low-level handling routines.
24 * This also contains the timer-interrupt handler, as well as all interrupts
25 * and faults that can result in a task-switch.
27 * NOTE: This code handles signal-recognition, which happens every time
28 * after a timer-interrupt and after each system call.
30 * NOTE: This code uses a convention that instructions in the delay slot
31 * of a transfer-control instruction are indented by an extra space, thus:
[all …]
/linux/arch/arm64/kvm/hyp/
H A Dhyp-entry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015-2018 - ARM Ltd
7 #include <linux/arm-smccc.h>
20 stp x2, x3, [sp, #-16]!
21 stp x4, x5, [sp, #-16]!
22 stp x6, x7, [sp, #-16]!
23 stp x8, x9, [sp, #-16]!
24 stp x10, x11, [sp, #-16]!
25 stp x12, x13, [sp, #-16]!
26 stp x14, x15, [sp, #-16]!
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/kernel/kprobes-test.c
9 * This file contains test code for ARM kprobes.
12 * supported instruction sets: ARM, 16-bit Thumb, and 32-bit Thumb. These tests
23 * The individual test cases are in kprobes-test-arm.c and kprobes-test-thumb.c
24 * which use the macros defined in kprobes-test.h. The rest of this
31 * -------------------
41 * post-handler of the test_before probe is used to modify the saved CPU
43 * pre-handler of the of the test_after probe saves a copy of the CPU
54 * flags value of stored in CPSR, and for Thumb code, different ITState.
[all …]

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