Lines Matching +full:bl +full:- +full:code +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
10 * Low-level exception handers, MMU support, and rewrite.
13 * Copyright (c) 1998-1999 TiVo, Inc.
23 * Copyright 2002-2005 MontaVista Software, Inc.
35 #include <asm/asm-offsets.h>
38 #include <asm/code-patching-asm.h>
42 /* As with the other PowerPC ports, it is expected that when code
46 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
47 * r4 - Starting address of the init RAM disk
48 * r5 - Ending address of the init RAM disk
49 * r6 - Start of kernel command line string (e.g. "mem=128")
50 * r7 - End of kernel command line string
74 addis r21,r21,(_stext - 0b)@ha
75 addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */
79 * We calculate our shift of offset from a 256M page.
87 subf r3,r5,r6 /* r3 = r6 - r5 */
90 bl relocate
93 bl init_cpu_state
96 * This is where the main kernel code starts.
111 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)
113 bl early_init
121 * r21 will contain the current offset of _stext
131 rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */
132 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
142 * virt_phys_offset = stext.run - kernstart_addr
150 * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
191 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
202 bl kasan_early_init
206 bl machine_init
207 bl MMU_init
233 * Interrupt vector entry code
362 /* Compute pgdir/pmd offset */
394 /* Re-load the faulting address */
401 /* The bailout. Restore registers to pre-exception conditions
461 /* Compute pgdir/pmd offset */
493 /* Re-load the faulting address */
500 /* The bailout. Restore registers to pre-exception conditions
514 * r10 - EA of fault
515 * r11 - PTE high word value
516 * r12 - PTE low word value
517 * r13 - TLB index
518 * cr7 - Result of comparison with PAGE_OFFSET
519 * MMUCR - loaded with proper value when we get here
524 rlwimi r11,r12,0,0,31-PAGE_SHIFT
538 rlwimi r10,r12,29,30,31 /* DIRTY,READ -> SW,SR position */
606 /* Compute pgdir/pmd offset */
612 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
642 2: /* The bailout. Restore registers to pre-exception conditions
693 /* Compute pgdir/pmd offset */
699 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
729 2: /* The bailout. Restore registers to pre-exception conditions
743 * r10 - free to use
744 * r11 - PTE high word value
745 * r12 - PTE low word value
746 * r13 - free to use
747 * cr7 - Result of comparison with PAGE_OFFSET
748 * MMUCR - loaded with proper value when we get here
753 rlwimi r11,r12,0,0,31-PAGE_SHIFT
758 rlwimi r10,r12,29,30,31 /* DIRTY,READ -> SW,SR position */
833 * We are still executing code at the virtual address
856 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
1003 bl init_cpu_state
1006 * is done in C code. We must be careful because our task
1010 * because only one CPU at a time can be in this code
1014 addi r1,r1,1024-STACK_FRAME_MIN_SIZE
1017 bl mmu_init_secondary
1027 addi r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE
1042 * We are still executing code at the virtual address
1047 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
1122 /* Word 1 - use r25. RPN is the same as the original entry */
1179 /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
1211 * current 32-bit kernel code isn't too happy with icache != dcache
1224 * Here we are back to code that is common between 44x and 47x
1231 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1235 * If the kernel was loaded at a non-zero 256 MB page, we need to