Lines Matching +full:bl +full:- +full:code +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
26 * Note that these macros must not contain any code which is not
82 bl putc
88 bl phex
101 kputc #'-'
105 kputc #'-'
110 kputc #'-'
154 * in little-endian form.
227 bl __hyp_stub_install @ get into SVC mode, reversibly
234 * Booting from Angel - need to enter SVC mode and disable
251 * be needed here - is there an Angel SWI call for this?
255 * some architecture specific code can be inserted
265 * We just need to get rid of any offset by aligning the
269 * different platforms - we have chosen 128MB to allow
288 * an offset from the same start of physical memory.
299 * Make sure we have some stack before calling C code.
300 * No GOT fixup has occurred yet, but none of the code we're
308 bl fdt_check_mem_start
319 * That means r4 < pc || r4 - 16k page directory > &_end.
345 * but someone could still run this code from RAM,
378 * yet, but none of the code we're about to call uses any
388 /* preserve 64-bit alignment */
402 bl atags_to_fdt
406 * pointed by r8. Try the typical 0x100 offset from start
426 * than the relocated code.
438 /* preserve 64-bit alignment */
455 * r4 - 16k page directory >= r10 -> OK
456 * r4 + image length <= address of wont_overwrite -> OK
475 * Bump to the next 256-byte boundary with the size of
476 * the relocation code added. This avoids overwriting
477 * ourself when the offset is small.
479 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
482 /* Get start of code we want to copy and align it down. */
501 bl __hyp_set_vectors
525 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
527 stmdb r9!, {r0 - r3, r10 - r12, lr}
530 /* Preserve offset to relocated code. */
535 bl cache_clean_flush
544 sub r0, r0, r1 @ calculate the delta offset
634 bl decompress_kernel
640 bl cache_clean_flush
641 bl cache_off
650 bl __hyp_set_vectors
665 .size LC0, . - LC0
668 LC1: .word .L_user_stack_end - LC1 @ sp
669 .word _edata - LC1 @ r6
670 .size LC1, . - LC1
673 .word _end - restart + 16384 + 1024*1024
676 .long (input_data_end - 4) - .
687 * dcache_line_size - get the minimum D-cache line size from the CTR register
735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
741 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
745 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
746 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
755 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
756 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
765 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
810 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
834 @ Enable unaligned access on v6, to allow better code generation
835 @ for the decompressor C code:
853 bl __setup_mmu
858 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
860 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
861 bl __common_mmu_cache_on
882 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
888 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
892 bic r6, r6, #1 << 31 @ 32-bit translation system
908 bl __setup_mmu
914 orr r0, r0, #0x1000 @ I-cache enable
915 bl __common_mmu_cache_on
925 mov r1, #-1
940 * entry and jumping to an instruction at the specified offset
942 * independent code.
946 * r3 = block offset
956 * On v7-M the processor id is located in the V7M_SCB_CPUID
958 * v7-M (if existant at all) we just return early here.
961 * use cp15 registers that are not implemented on v7-M.
979 * - CPU ID match
980 * - CPU ID mask
981 * - 'cache on' method instruction
982 * - 'cache off' method instruction
983 * - 'cache flush' method instruction
1031 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
1134 .size proc_types, . - proc_types
1137 * If you get a "non-constant expression in ".if" statement"
1142 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
1165 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1166 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1346 .size phexbuf, . - phexbuf
1392 bl phex
1394 bl putc
1396 bl putc
1399 bl phex
1409 bl putc
1457 adr r1, 0f @ clean the region of code we
1458 bl cache_clean_flush @ may run with the MMU off
1464 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1467 @ U-Boot might decide to enter the EFI stub in HYP mode
1484 @ issued from HYP mode take us to the correct handler code. We
1501 bl __hyp_stub_install @ install HYP stub vectors
1515 bl cache_clean_flush
1525 0: .long .L_user_stack_end - .