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/linux/drivers/gpu/drm/msm/registers/display/
H A Dedp.xml23 <bitfield name="ENABLE" pos="0" type="boolean"/>
24 <bitfield name="RESET" pos="1" type="boolean"/>
28 <bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
29 <bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>
30 <bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>
31 <bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>
32 <bitfield name="PRBS7" pos="4" type="boolean"/>
33 <bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
34 <bitfield name="SEND_VIDEO" pos="6" type="boolean"/>
35 <bitfield name="PUSH_IDLE" pos="7" type="boolean"/>
[all …]
H A Dmdp4.xml66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
67 <bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/>
68 <bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/>
69 <bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/>
70 <bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/>
71 <bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/>
72 <bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/>
73 <bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/>
74 <bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/>
75 <bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/>
[all …]
H A Ddsi_phy_28nm.xml31 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
34 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
37 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
40 <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
43 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
46 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
49 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
52 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
55 <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
58 <bitfield name="TA_GO" low="0" high="2" type="uint"/>
[all …]
H A Dmdss.xml9 <bitfield name="STEP" low="0" high="15" type="uint"/>
10 <bitfield name="MINOR" low="16" high="27" type="uint"/>
11 <bitfield name="MAJOR" low="28" high="31" type="uint"/>
15 <bitfield name="INTR_MDP" pos="0" type="boolean"/>
16 <bitfield name="INTR_DSI0" pos="4" type="boolean"/>
17 <bitfield name="INTR_DSI1" pos="5" type="boolean"/>
18 <bitfield name="INTR_HDMI" pos="8" type="boolean"/>
19 <bitfield name="INTR_EDP" pos="12" type="boolean"/>
25 <bitfield name="UBWC_SWIZZLE" low="0" high="2"/>
26 <bitfield name="UBWC_BANK_SPREAD" pos="3"/>
[all …]
H A Ddsi_phy_14nm.xml13 <bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
14 <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
17 <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
20 <bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
35 <bitfield name="PLL_START" pos="0" type="boolean"/>
38 <bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
45 <bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
48 <bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
55 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
58 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
[all …]
H A Ddsi_phy_20nm.xml31 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
34 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
37 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
40 <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
43 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
46 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
49 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
52 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
55 <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
58 <bitfield name="TA_GO" low="0" high="2" type="uint"/>
[all …]
H A Ddsi_phy_28nm_8960.xml27 <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
30 <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
33 <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
39 <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
42 <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
45 <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
48 <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
51 <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
54 <bitfield name="TA_GO" low="0" high="2" type="uint"/>
55 <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
[all …]
H A Dmdp_common.xml73 <bitfield name="HEIGHT" low="16" high="31" type="uint"/>
74 <bitfield name="WIDTH" low="0" high="15" type="uint"/>
78 <bitfield name="Y" low="16" high="31" type="uint"/>
79 <bitfield name="X" low="0" high="15" type="uint"/>
83 <bitfield name="ELEM0" low="0" high="7"/>
84 <bitfield name="ELEM1" low="8" high="15"/>
85 <bitfield name="ELEM2" low="16" high="23"/>
86 <bitfield name="ELEM3" low="24" high="31"/>
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da3xx.xml572 <bitfield name="HI_BUSY" pos="0" type="boolean"/>
573 <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
574 <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
575 <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
576 <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
577 <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
578 <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
579 <bitfield name="RB_BUSY" pos="18" type="boolean"/>
580 <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
581 <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
[all …]
H A Da2xx.xml1031 <bitfield name="COLUMN" low="0" high="2" type="uint"/>
1032 <bitfield name="ROW" low="3" high="5" type="uint"/>
1033 <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
1055 <bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
1056 <bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
1057 <bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
1058 <bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
1059 <bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
1060 <bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
1061 <bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
[all …]
H A Da6xx.xml37 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
38 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
39 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
40 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
41 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
42 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
43 <bitfield name="CP_SW" pos="8" type="boolean"/>
44 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
45 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
46 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
[all …]
H A Da6xx_gmu.xml11 <bitfield name="BUSY_IGN_AHB" pos="23"/>
12 <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
16 <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
17 <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
18 <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
19 <bitfield name="DCVS_SET_MASK" pos="23"/>
20 <bitfield name="DCVS_CHECK_MASK" pos="31"/>
21 <bitfield name="DCVS_CLEAR_MASK" pos="31"/>
22 <bitfield name="GPU_SET_MASK" pos="18"/>
23 <bitfield name="GPU_CHECK_MASK" pos="26"/>
[all …]
H A Da4xx.xml879 <bitfield name="WIDTH" low="0" high="13" type="uint"/>
880 <bitfield name="HEIGHT" low="16" high="29" type="uint"/>
893 <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
894 <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
895 <bitfield name="ENABLE_GMEM" pos="16" type="boolean"/>
898 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
901 <bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/>
904 <bitfield name="DISABLE" pos="12" type="boolean"/>
905 <bitfield name="SAMPLES" low="13" high="15" type="uint"/>
908 <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
[all …]
/linux/rust/kernel/
H A Dbitfield.rs5 //! The [`bitfield!`](kernel::bitfield!) macro declares integer types that are split into distinct
12 //! use kernel::bitfield;
15 //! bitfield! {
50 //! bitfield! {
80 //! The macro generates the bitfield type, [`From`] and [`Into`] implementations for its storage
95 //! Field identifiers are used to generate methods and associated constants on the bitfield type.
101 //! any field in the same bitfield. The following prefixes are thus reserved for field identifiers:
119 //! use kernel::bitfield;
121 //! bitfield! {
140 //! use kernel::bitfield;
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.h59 * rec - [IN] The bitfield values to write to the table row.
77 * rec - [IN] The bitfield values to write to the table row.
95 * rec - [IN] The bitfield values to write to the table row.
113 * rec - [IN] The bitfield values to write to the table row.
131 * rec - [IN] The bitfield values to write to the table row.
149 * rec - [IN] The bitfield values to write to the table row.
167 * rec - [IN] The bitfield values to write to the table row.
185 * rec - [IN] The bitfield values to write to the table row.
203 * rec - [IN] The bitfield values to write to the table row.
221 * rec - [IN] The bitfield values to write to the table row.
[all …]
/linux/include/linux/clk/
H A Dti.h31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
52 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
53 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
55 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
[all …]
/linux/tools/include/linux/
H A Dbitfield.h15 * Bitfield access macros
103 * FIELD_PREP() - prepare a bitfield element
108 * be combined with other fields of the bitfield using logical OR.
117 * FIELD_GET() - extract a bitfield element
119 * @_reg: value of entire bitfield
122 * bitfield passed in as @_reg by masking and shifting it down.
132 extern void __compiletime_error("bad bitfield mask")
/linux/tools/testing/selftests/bpf/progs/
H A Dverifier_bitfield_write.c25 __description("single CO-RE bitfield roundtrip")
39 __description("multiple CO-RE bitfield roundtrip")
60 __description("adjacent CO-RE bitfield roundtrip")
80 __description("multibyte CO-RE bitfield roundtrip")
H A Dcore_reloc_types.h725 /* bitfield read results, all as plain integers */
763 /* turn bitfield into non-bitfield and vice versa */
765 uint64_t ub1; /* 3 -> 64 non-bitfield */
766 uint8_t ub2; /* 20 -> 8 non-bitfield */
767 int64_t ub7 __bpf_aligned; /* 7 -> 64 non-bitfield signed */
768 int64_t sb4 __bpf_aligned; /* 4 -> 64 non-bitfield signed */
769 uint64_t sb20 __bpf_aligned; /* 20 -> 16 non-bitfield unsigned */
770 int32_t u32: 20; /* 32 non-bitfield -> 20 bitfield */
[all...]
H A Dbtf_dump_test_case_bitfields.c4 * BTF-to-C dumper tests for bitfield.
59 short b; /* combined with previous bitfield */
64 int e; /* combined with previous bitfield */
/linux/drivers/mux/
H A Dmmio.c3 * MMIO register bitfield-controlled multiplexer driver
127 dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n", in mux_mmio_probe()
137 dev_err(dev, "bitfield %d: invalid mask 0x%x\n", in mux_mmio_probe()
145 dev_err(dev, "bitfield %d: failed to allocate: %d\n", in mux_mmio_probe()
157 dev_err(dev, "bitfield: %d: out of range idle state %d\n", in mux_mmio_probe()
222 MODULE_DESCRIPTION("MMIO register bitfield-controlled multiplexer driver");
/linux/include/linux/net/intel/libie/
H A Drx.h27 * bitfield struct.
35 * libie_rx_pt_parse - convert HW packet type to software bitfield structure
40 * Return: parsed bitfield struct corresponding to the provided ptype.
/linux/include/linux/
H A Djournal-head.h41 * NOTE: We *cannot* combine this with b_modified into a bitfield
43 * very unuseful) make 64-bit accesses to the bitfield and clobber
44 * b_jcount if its update races with bitfield modification.
/linux/arch/arm/mach-versatile/
H A Dspc.c98 * It corresponds to A15 processors MPIDR[15:8] bitfield
142 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
143 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
175 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
176 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
197 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
225 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
226 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
/linux/arch/arm/mach-omap2/
H A Dcm33xx.c28 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
82 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
86 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
102 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
116 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
117 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)

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