Home
last modified time | relevance | path

Searched +full:bit0 +full:- +full:7 (Results 1 – 25 of 167) sorted by relevance

1234567

/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
46 /* 0xc00[7:0] = 4 turn off 3-wire */}, \
49 /* 0xe00[7:0] = 4 turn off 3-wire */}, \
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
61 /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/}, \
82 /* gpio 0~7 output same value as input ?? */}, \
85 /* gpio0~7 output mode */}, \
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
10 0: POFF--Power Off
11 1: PDN--Power Down
12 2: CARDEMU--Card Emulation
13 3: ACT--Active Mode
14 4: LPS--Low Power State
15 5: SUS--Suspend
42 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b…
47 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB …
[all …]
H A Drtw_ht.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
13 u8 ampdu_enable;/* for enable Tx A-MPDU */
14 u8 tx_amsdu_enable;/* for enable Tx A-MSDU */
27 /* for processing Tx A-MPDU */
64 #define LDPC_HT_ENABLE_RX BIT0
68 #define STBC_HT_ENABLE_RX BIT0
72 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
79 #define GET_HT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
H A Dhal_com_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
32 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
33 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
112 /* Format for offset 540h-542h: */
114 /* [7:4]: Reserved. */
119 /* |<--Setup--|--Hold------------>| */
120 /* --------------|---------------------- */
124 /* Described by Designer Tim and Bruce, 2011-01-14. */
156 #define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
[all …]
/linux/Documentation/input/devices/
H A Dsentelic.rst8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
30 |---------------| |---------------| |---------------| |---------------|
39 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
42 Byte 4: Bit3~Bit0 => the scrolling wheel's movement since the last data report.
43 valid values, -8 ~ +7
[all …]
/linux/Documentation/driver-api/mtd/
H A Dnand_ecc.rst2 NAND Error-correction Code
11 After that the speed was increased by 35-40%.
45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
52 byte 255: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp5 ... rp15
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
[all …]
/linux/Documentation/leds/
H A Dleds-mlxcpld.rst10 -----------
14 - mlxcpld:fan1:green
15 - mlxcpld:fan1:red
16 - mlxcpld:fan2:green
17 - mlxcpld:fan2:red
18 - mlxcpld:fan3:green
19 - mlxcpld:fan3:red
20 - mlxcpld:fan4:green
21 - mlxcpld:fan4:red
22 - mlxcpld:psu:green
[all …]
/linux/drivers/video/fbdev/via/
H A Ddvi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
41 switch (viaparinfo->chip_info->gfx_chip_name) { in viafb_tmds_trasmitter_identify()
45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
63 /* SR3E[1]Multi-function selection: in viafb_tmds_trasmitter_identify()
71 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS; in viafb_tmds_trasmitter_identify()
72 viaparinfo->chip_info-> in viafb_tmds_trasmitter_identify()
[all …]
H A Dlcd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
25 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
28 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
32 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
34 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
75 viaparinfo->lvds_setting_info2->lcd_panel_hres = in viafb_init_lcd_size()
76 viaparinfo->lvds_setting_info->lcd_panel_hres; in viafb_init_lcd_size()
[all …]
H A Dhw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
16 {41, 100, 7, 0},
29 {31, 84, 7, 1},
35 {90, 90, 7, 2},
40 {99, 99, 7, 3}
70 {174, 174, 7, 2},
96 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dedid.h2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
62 * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
69 * port selection. value of bit0 - bit2 corresponds to the GPIO registers.
74 * bit0 is the direction bit: 1 is read; 0 is write.
75 * bit1 - bit7 is target 7-bit address.
76 * bit16 - bit24 total byte count (ignore?)
81 * bit0 - bit8 current byte count
/linux/include/uapi/linux/
H A Dioam6.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
48 __u8 remlen:7,
62 bit0:1, member
91 remlen:7;
97 __u32 bit0:1, member
/linux/drivers/scsi/
H A Ddc395x.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* (SCSI chip set used Tekram ASIC TRM-S1040) */
28 /* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */
76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
[all …]
/linux/drivers/input/touchscreen/
H A Dwdt87xx_i2c.c4 * Copyright (c) 2015 Weida Hi-Tech Co., Ltd.
59 #define FINGER_EV_V1_SIZE 7
193 .addr = client->addr, in wdt87xx_i2c_xfer()
199 .addr = client->addr, in wdt87xx_i2c_xfer()
208 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in wdt87xx_i2c_xfer()
210 error = ret < 0 ? ret : -EIO; in wdt87xx_i2c_xfer()
211 dev_err(&client->dev, "%s: i2c transfer failed: %d\n", in wdt87xx_i2c_xfer()
230 dev_err(&client->dev, "get desc failed: %d\n", error); in wdt87xx_get_desc()
235 dev_err(&client->dev, "unexpected response to get desc: %d\n", in wdt87xx_get_desc()
237 return -EINVAL; in wdt87xx_get_desc()
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dtm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
7 * the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h49 * bit(7:2): real revision
103 #define ALX_PMCTRL_L1_BUFSRX_EN BIT(7)
121 #define ALX_MASTER_SYSALVTIMER_EN BIT(7)
125 /* bit0: MAC & DMA reset */
142 #define ALX_PHY_CTRL_IDDQ BIT(7)
145 /* bit0: out of dsp RST state */
168 #define ALX_MDIO_CLK_SEL_25MD128 7
266 #define ALX_MAC_CTRL_PCRCE BIT(7)
327 #define ALX_TXQ0_LSO_8023_EN BIT(7)
338 #define ALX_TXQ1_JUMBO_TSO_TH (7*1024)
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
119 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
120 #define ATOM_INIT (ATOM_DISABLE+7)
136 #define ATOM_TV_PAL60 7
156 // Bit0:{=0:single, =1:dual},
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
[all …]
/linux/include/video/
H A Dpxa168fb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define PIN_MODE_SMART_16_SPI 7
32 /* default fb buffer size WVGA-32bits */
37 * bit0 is for rb swap.
47 #define PIX_FMT_BGR888UNPACK 7
97 * Dumb panel -- assignment of R/G/B component info to the 24
104 * Dumb panel -- GPIO output data.
110 * Dumb panel -- configurable output signal polarity.
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
78 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
84 /* 0: Type-1, */
85 /* 1: Type-2, */
86 /* 2: Type-3, */
87 /* 3: Type-4 */
89 /* Bit0: 16bpp (not supported in LNC), */
94 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
107 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
[all …]
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
38 …(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_…
43 …amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.ato…
47 bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
89 if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, in bios_cmd_table_para_revision()
125 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3; in init_dig_encoder_control()
128 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4; in init_dig_encoder_control()
132 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5; in init_dig_encoder_control()
153 struct cmd_tbl *cmd_tbl = &bp->cmd_tbl; in init_encoder_control_dig_v1()
156 cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1; in init_encoder_control_dig_v1()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
105 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
106 #define ATOM_INIT (ATOM_DISABLE+7)
127 #define ATOM_TV_PAL60 7
146 /* Bit0:{=0:single, =1:dual},
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
358 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
362 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_debugfs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
29 #define HCLGE_DBG_DFX_NCSI_OFFSET 7
54 u8 bit0 : 1, member
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.h2 * Copyright (c) 2010-2011 Atheros Communications Inc.
27 /* 16-bit offset location start of calibration struct */
66 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET
67 * (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
68 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
71 #define NOISE_PWR_DATA_OFFSET -90
200 * bit0 - enable tx temp comp
201 * bit1 - enable tx volt comp
202 * bit2 - enable fastClock - default to 1
203 * bit3 - enable doubling - default to 1
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,mcp23s08.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
22 - microchip,mcp23s08
23 - microchip,mcp23s17
24 - microchip,mcp23s18
25 - microchip,mcp23008
26 - microchip,mcp23017
[all …]
/linux/include/linux/mfd/
H A Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
104 /* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
129 #define LP87565_INT_GPIO BIT(7)
159 #define LP87565_BUCK1_STAT BIT(7)
166 #define LP87565_BUCK3_STAT BIT(7)
173 #define LPL87565_GPIO_MASK BIT(7)
200 #define LP87565_HALF_DAY BIT(7)
[all …]

1234567