| /freebsd/sys/dev/pms/RefTisa/sallsdk/spc/ |
| H A D | spcdefs.h | 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
42 #define SPC_MSGU_CFG_TABLE_UPDATE 0x001 /* Inbound doorbell bit0 */
64 bit32 Header; /* Bits [11:0] - Message operation code */
65 /* Bits [15:12] - Message Category */
66 … /* Bits [21:16] - Outboundqueue ID for the operation completion message */
67 /* Bits [23:22] - Reserved */
68 … /* Bits [28:24] - Buffer Count, indicates how many buffer are allocated for the massage */
69 /* Bits [30:29] - Reserved */
70 /* Bits [31] - Message Valid bit */
96 bit8 Signature[4]; /**< DW0 signature - Indicate coherent table */
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| H A D | mpi.h | 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
190 bit32 BunchStarts_QPending; // un-started bunched IOs on queue
202 /* bit0-7 inbound normal priority process depth */
203 /* bit8-15 inbound high priority process depth */
204 /* bit16-23 OQ number to receive GENERAL_EVENT Notification */
205 /* bit24-31 reserved */
207 /* bit0-7 outbound queue number of SAS_HW event for PortId 0 */
208 /* bit8-15 outbound queue number of SAS_HW event for PortId 1 */
209 /* bit16-23 outbound queue number of SAS_HW event for PortId 2 */
210 /* bit24-31 outbound queue number of SAS_HW event for PortId 3 */
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| H A D | sahwreg.h | 2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
34 /* Message Unit Registers - BAR0(0x10), BAR0(win) */
36 /* i2o=1 space register offsets - MU_I2O_ENABLE */
52 /* i2o=0 space register offsets - ~MU_I2O_ENABLE */
53 #define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */
58 #define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */
85 #define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound D…
86 #define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound D…
87 …Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Cle…
88 …Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Cle…
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| /freebsd/sys/contrib/edk2/Include/IndustryStandard/ |
| H A D | Acpi60.h | 4 Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
194 #define EFI_ACPI_6_0_PM_PROFILE_PERFORMANCE_SERVER 7
201 #define EFI_ACPI_6_0_LEGACY_DEVICES BIT0
212 #define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0
219 #define EFI_ACPI_6_0_WBINVD BIT0
268 #define EFI_ACPI_6_0_S4BIOS_F BIT0
275 #define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0
306 #define EFI_ACPI_6_0_PCAT_COMPAT BIT0
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| H A D | Acpi51.h | 4 Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
5 Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
194 #define EFI_ACPI_5_1_PM_PROFILE_PERFORMANCE_SERVER 7
201 #define EFI_ACPI_5_1_LEGACY_DEVICES BIT0
212 #define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0
219 #define EFI_ACPI_5_1_WBINVD BIT0
268 #define EFI_ACPI_5_1_S4BIOS_F BIT0
275 #define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0
306 #define EFI_ACPI_5_1_PCAT_COMPAT BIT0
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| H A D | Acpi50.h | 4 Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
5 Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
311 #define EFI_ACPI_5_0_PM_PROFILE_PERFORMANCE_SERVER 7
318 #define EFI_ACPI_5_0_LEGACY_DEVICES BIT0
329 #define EFI_ACPI_5_0_WBINVD BIT0
378 #define EFI_ACPI_5_0_S4BIOS_F BIT0
385 #define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0
416 #define EFI_ACPI_5_0_PCAT_COMPAT BIT0
455 #define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0
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| H A D | Acpi40.h | 4 Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
181 #define EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER 7
187 #define EFI_ACPI_4_0_LEGACY_DEVICES BIT0
197 #define EFI_ACPI_4_0_WBINVD BIT0
244 #define EFI_ACPI_4_0_S4BIOS_F BIT0
251 #define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0
282 #define EFI_ACPI_4_0_PCAT_COMPAT BIT0
319 #define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0
370 /// Non-Maskable Interrupt Source Structure
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| H A D | Acpi10.h | 4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
142 UINT8 Name : 7;
197 /// 24-Bit Memory Range Descriptor
209 /// 32-Bit Memory Range Descriptor
221 /// Fixed 32-Bit Fixed Memory Range Descriptor
384 #define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0
478 #define EFI_ACPI_1_0_WBINVD BIT0
506 #define EFI_ACPI_1_0_S4BIOS_F BIT0
510 /// must be defined in a platform-specific manner.
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| H A D | Acpi30.h | 4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
21 /// C-state Coordination Types
22 /// See s8.4.2.2 _CSD (C-State Dependency)
30 // See s8.4.4.5 _PSD (P-State Dependency)
232 #define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7
238 #define EFI_ACPI_3_0_LEGACY_DEVICES BIT0
248 #define EFI_ACPI_3_0_WBINVD BIT0
293 #define EFI_ACPI_3_0_S4BIOS_F BIT0
324 #define EFI_ACPI_3_0_PCAT_COMPAT BIT0
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Language/ObjC/ |
| H A D | CF.cpp | 1 //===-- CF.cpp ------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
39 stream.Printf("%04d-%02d-%02d %02d:%02d:%02d %s", tm_date->tm_year + 1900, in CFAbsoluteTimeSummaryProvider()
40 tm_date->tm_mon + 1, tm_date->tm_mday, tm_date->tm_hour, in CFAbsoluteTimeSummaryProvider()
41 tm_date->tm_min, tm_date->tm_sec, buffer.c_str()); in CFAbsoluteTimeSummaryProvider()
59 runtime->GetClassDescriptor(valobj)); in CFBagSummaryProvider()
61 if (!descriptor.get() || !descriptor->IsValid()) in CFBagSummaryProvider()
64 uint32_t ptr_size = process_sp->GetAddressByteSize(); in CFBagSummaryProvider()
74 if (descriptor->IsCFType()) { in CFBagSummaryProvider()
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300eep.h | 32 /* FreeBSD extras - should be in ah_eeprom.h ? */
88 ar9300_eeprom_template_xb114 = 7,
111 // 16-bit offset location start of calibration struct
146 (u_int8_t)((is_2ghz) ? ((freq) - 2300) : (((freq) - 4800) / 5))
153 #define OSPREY_NUM_ANT_CHAIN_FIELDS 7
165 #define OSPREY_3_CHAINMASK 7
214 1,1,6,7,8,
249 u_int8_t feature_enable; //bit0 - enable tx temp comp
250 //bit1 - enable tx volt comp
251 //bit2 - enable fastClock - default to 1
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| H A D | ar9300template_wasp_k31.h | 53 0x0c, //featureEnable; //bit0 - enable tx temp comp
54 //bit1 - enable tx volt comp
55 //bit2 - enable fastClock - default to 1
56 //bit3 - enable doubling - default to 1
57 //bit4 - enable internal regulator - default to 0
58 0, //miscConfiguration: bit0 - turn down drivestrength
79 …{-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per ch…
88 -30, // adcDesiredSize; // 1
155 //1L-5L,5S,11L,11S
162 //6-24,36,48,54
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| H A D | ar9300template_ap121.h | 44 {"ap121-010-00000"},
59 0x0d, //feature_enable; //bit0 - enable tx temp comp
60 //bit1 - enable tx volt comp
61 //bit2 - enable fastClock - default to 1
62 //bit3 - enable doubling - default to 1
63 //bit4 - enable internal regulator - default to 0
64 //bit5 - enable paprd -- default to 0
65 0, //misc_configuration: bit0 - turn down drivestrength
86 …{-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per…
95 -30, // adcDesiredSize; // 1
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| H A D | ar9300template_cus157.h | 44 {"cus157-030-f0000"},
59 0x0d, //featureEnable; //bit0 - enable tx temp comp
60 //bit1 - enable tx volt comp
61 //bit2 - enable fastClock - default to 1
62 //bit3 - enable doubling - default to 1
63 //bit4 - enable internal regulator - default to 0
64 //bit5 - enable paprd -- default to 0
65 0, //miscConfiguration: bit0 - turn down drivestrength
86 …{-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per ch…
95 -30, // adcDesiredSize; // 1
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | nvm-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_regulatory_and_nvm_subcmd_ids - regulatory/NVM commands
61 * enum iwl_nvm_access_op - NVM access opcode
71 * enum iwl_nvm_access_target - target of the NVM_ACCESS_CMD
83 * enum iwl_nvm_section_type - section types for NVM_ACCESS_CMD
105 * struct iwl_nvm_access_cmd - Request the device to send an NVM section
123 * struct iwl_nvm_access_resp - response to NVM_ACCESS_CMD
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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| /freebsd/sys/dev/hptmv/ |
| H A D | hptintf.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
54 * Logical device --- a device that can be accessed by OS.
55 * Physical device --- device attached to the controller.
78 * GUI will treat all array as 1-level RAID. No RAID0/1 or RAID1/0.
86 #define AT_JBOD 7
124 #define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */
136 #define DEVICE_FLAG_SATA 0x00000010 /* S-ATA device */
154 #define AS_INITIALIZE_START 7
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-370-synology-ds213j.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-binding
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| H A D | armada-xp-synology-ds414.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-binding
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| /freebsd/crypto/openssl/crypto/ml_kem/ |
| H A D | ml_kem.c | 2 * Copyright 2024-2025 The OpenSSL Project Authors. All Rights Reserved.
23 # error "ML-KEM keygen seed length != shared secret + random bytes length"
26 # error "Invalid unequal lengths of ML-KEM shared secret and random inputs"
33 /* Handy function-like bit-extraction macros */
34 #define bit0(b) ((b) & 1) macro
38 * 12 bits are sufficient to losslessly represent values in [0, q-1].
39 * INVERSE_DEGREE is (n/2)^-1 mod q; used in inverse NTT.
42 #define INVERSE_DEGREE (ML_KEM_PRIME - 2 * 13)
51 * Return whether a value that can only be 0 or 1 is non-zero, in constant time
53 * zeros otherwise (twos-complement arithmentic assumed for unsigned values).
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| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_irig.c | 2 * refclock_irig - audio IRIG-B/E demodulator/decoder
26 * Audio IRIG-B/E demodulator/decoder
29 * IRIG-B/E signals commonly produced by GPS receivers and other timing
30 * devices. The IRIG signal is an amplitude-modulated carrier with
31 * pulse-width modulated data bits. For IRIG-B, the carrier frequency is
32 * 1000 Hz and bit rate 100 b/s; for IRIG-E, the carrier frequenchy is
37 * kHz and mu-law companding. This is the same standard as used by the
43 * The program processes 8000-H
187 #define BIT0 global() macro
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| /freebsd/sys/contrib/dev/athk/ath12k/ |
| H A D | dp.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
255 #define DP_INVALID_BANK_ID -1
332 * - reo_cmd_list
333 * - reo_cmd_cache_flush_list
334 * - reo_cmd_cache_flush_count
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | dp.h | 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
236 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
282 * - reo_cmd_list
283 * - reo_cmd_cache_flush_list
284 * - reo_cmd_cache_flush_count
333 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
356 /* host -> target HTT_SRING_SETUP message
366 * |31 24|23 20|19|18 16|15|14 8|7 0|
367 * |--------------- +-----------------+----------------+------------------|
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| /freebsd/contrib/tcpdump/ |
| H A D | print-802_11.c | 27 #include "netdissect-stdinc.h"
123 { CTRL_PS_POLL, "Power Save-Poll" },
124 { CTRL_RTS, "Request-To-Send" },
125 { CTRL_CTS, "Clear-To-Send" },
127 { CTRL_CF_END, "CF-End" },
128 { CTRL_END_ACK, "CF-End+CF-Ack" },
151 * bits - CF-Ack, CF-Poll, Null (means the frame doesn't actually have
205 uint8_t text[254]; /* 1-253 + 1 for null */
244 /* reserved 7 */
428 * the MCS index (0-76);
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| /freebsd/sys/dev/hptrr/ |
| H A D | hptintf.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 * Logical device --- a device that can be accessed by OS.
70 * Physical device --- device attached to the controller.
93 * GUI will treat all array as 1-level RAID. No RAID0/1 or RAID1/0.
104 #define AT_JBOD 7
153 #define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */
192 #define AS_INITIALIZE_START 7
208 #define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00)
216 #define HPT_CTL_CODE_WIN32_TO_IOP(x) ((((x) & 0xffff)>>2)-0x900)
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