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/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphy_qmath.c1 // SPDX-License-Identifier: ISC
9 * Description: This function make 16 bit unsigned multiplication.
10 * To fit the output into 16 bits the 32 bit multiplication result is right
19 * Description: This function make 16 bit multiplication and return the result
22 * is done to remove the extra sign bit formed due to the multiplication.
23 * When both the 16bit inputs are 0x8000 then the output is saturated to
38 * Description: This function add two 32 bit numbers and return the 32bit
55 * Description: This function add two 16 bit numbers and return the 16bit
74 * Description: This function make 16 bit subtraction and return the 16bit
81 s32 temp = (s32) op1 - (s32) op2; in qm_sub16()
[all …]
/linux/drivers/gpio/
H A Dgpio-tangier.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/pinctrl/pinconf-generic.h>
30 #include "gpio-tangier.h"
46 * struct tng_gpio_context - Context to be saved during suspend-resume
69 return priv->reg_base + reg + reg_offset * 4; in gpio_reg()
73 unsigned int reg, u8 *bit) in gpio_reg_and_bit() argument
77 u8 shift = offset % 32; in gpio_reg_and_bit() local
79 *bit = shift; in gpio_reg_and_bit()
80 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit()
86 u8 shift; in tng_gpio_get() local
[all …]
/linux/include/linux/
H A Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-gate-grf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Certain clocks on Rockchip are "gated" behind an additional register bit
12 #include <linux/clk-provider.h>
21 unsigned int shift; member
30 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0; in rockchip_gate_grf_enable()
31 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_enable()
34 ret = regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_enable()
35 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_enable()
43 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift); in rockchip_gate_grf_disable()
44 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_disable()
[all …]
/linux/tools/include/linux/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 * Defined here because those may be needed by architecture-specific static
52 #include <asm-generic/bitops.h>
54 #define for_each_set_bit(bit, addr, size) \ argument
55 for ((bit) = find_first_bit((addr), (size)); \
56 (bit) < (size); \
57 (bit) = find_next_bit((addr), (size), (bit)
59 for_each_clear_bit(bit,addr,size) global() argument
65 for_each_set_bit_from(bit,addr,size) global() argument
87 rol32(__u32 word,unsigned int shift) rol32() argument
99 __u8 shift = 63 - index; sign_extend64() local
[all...]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_leds.c1 // SPDX-License-Identifier: GPL-2.0
16 #define IGC_LEDCTL_LED0_BLINK BIT(7)
19 #define IGC_LEDCTL_LED1_BLINK BIT(15)
22 #define IGC_LEDCTL_LED2_BLINK BIT(23)
33 (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK_1000) | \
34 BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK_10) | \
35 BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX))
38 (BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX))
50 u32 *mask, u32 *shift, u32 *blink) in igc_led_select() argument
55 *shift = IGC_LEDCTL_LED0_MODE_SHIFT; in igc_led_select()
[all …]
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dkeystone-pll.txt9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A Dbitfield.h10 * Purpose Definition of macros to operate on bit fields.
29 * The macro "Fld" encodes a bit field, given its size and its shift value
30 * with respect to bit 0.
33 * A more intuitive way to encode bit fields would have been to use their
34 * mask. However, extracting size and shift value information from a bit
35 * field's mask is cumbersome and might break the assembler (255-character
36 * line-size limit).
39 * Size Size of the bit field, in number of bits.
40 * Shft Shift value of the bit field with respect to bit 0.
43 * Fld Encoded bit field.
[all …]
/linux/tools/testing/shared/
H A Dshared.mk1 # SPDX-License-Identifier: GPL-2.0
4 CFLAGS += -I../shared -I. -I../../include -I../../arch/$(SRCARCH)/include \
5 -I../../../lib -g -Og -Wall \
6 -D_LGPL_SOURCE -fsanitize=address -fsanitize=undefined
8 LDFLAGS += -fsanitize=address -fsanitize=undefined
9 LDLIBS += -lpthread -lurcu
11 SHARED_OFILES = xarray-shared.o radix-tree.o idr.o linux.o $(LIBS)
13 SHARED_DEPS = Makefile ../shared/shared.mk ../shared/*.h generated/map-shift.h \
14 generated/bit-length.h generated/autoconf.h \
20 ../../../include/linux/radix-tree.h \
[all …]
/linux/arch/arm/mach-omap2/
H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
26 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
27 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
28 * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
29 * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
30 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
31 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
32 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
[all …]
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
99 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst, in omap4_prminst_is_hardreset_asserted() argument
105 v &= 1 << shift; in omap4_prminst_is_hardreset_asserted()
[all …]
/linux/arch/sh/boards/mach-x3proto/
H A Dilsel.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/boards/mach-x3proto/ilsel.c
5 * Helper routines for SH-X3 proto board ILSEL.
7 * Copyright (C) 2007 - 2010 Paul Mundt
21 * ILSEL0 - 0xb8100004 [ Levels 1 - 4 ]
22 * ILSEL1 - 0xb8100006 [ Levels 5 - 8 ]
23 * ILSEL2 - 0xb8100008 [ Levels 9 - 12 ]
24 * ILSEL3 - 0xb810000a [ Levels 13 - 15 ]
34 * Supported levels are 1 - 15 spread across ILSEL0 - ILSEL4, mapping
37 * 1:1 mapping between the bit position and the IRQ number.
[all …]
/linux/arch/sparc/lib/
H A Dudivdi3.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 save %sp,-104,%sp
24 addxcc %o1,%o1,%o1 ! shift n1n0 and a q-bit in lsb
31 addxcc %o1,%o1,%o1 ! shift n1n0 and a q-bit in lsb
40 addcc %o1,%o1,%o1 ! shift n1n0 and a 0-bit in lsb
62 addxcc %o2,%o2,%o2 ! shift n1n0 and a q-bit in lsb
69 addxcc %o2,%o2,%o2 ! shift n1n0 and a q-bit in lsb
78 addcc %o2,%o2,%o2 ! shift n1n0 and a 0-bit in lsb
88 addxcc %o1,%o1,%o1 ! shift n1n0 and a q-bit in lsb
95 addxcc %o1,%o1,%o1 ! shift n1n0 and a q-bit in lsb
[all …]
/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shif in sprd_mcdt_dac_dma_enable()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; sprd_mcdt_dac_dma_ack_select() local
320 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; sprd_mcdt_adc_dma_ack_select() local
342 u32 reg, shift; sprd_mcdt_chan_fifo_sts() local
395 u32 shift = MCDT_ADC_FIFO_SHIFT + channel; sprd_mcdt_adc_fifo_clear() local
456 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_en() local
481 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_clear() local
503 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_sts() local
[all...]
/linux/drivers/clk/mxs/
H A Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
13 * struct clk_frac - mxs fractional divider clock
16 * @shift: the divider bit shift
17 * @width: the divider bit width
18 * @busy: busy bit shift
20 * The clock is an adjustable fractional divider with a busy bit to wait
26 u8 shift; member
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
23 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_leds.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #define RTL8168_LED_CTRL_OPTION2 BIT(15)
16 #define RTL8168_LED_CTRL_ACT BIT(3)
17 #define RTL8168_LED_CTRL_LINK_1000 BIT(2)
18 #define RTL8168_LED_CTRL_LINK_100 BIT(1)
19 #define RTL8168_LED_CTRL_LINK_10 BIT(0)
21 #define RTL8125_LED_CTRL_ACT BIT(9)
22 #define RTL8125_LED_CTRL_LINK_2500 BIT(5)
23 #define RTL8125_LED_CTRL_LINK_1000 BIT(3)
24 #define RTL8125_LED_CTRL_LINK_100 BIT(1)
[all …]
/linux/arch/m68k/fpsp040/
H A Dround.S21 | round --- round result according to precision/mode
36 | a0 is preserved and the g-r-s bits in d0 are cleared.
37 | The result is not typed - the tag field is invalid. The
40 | The INEX bit of USER_FPSR will be set if the rounded result was
41 | inexact (i.e. if any of the g-r-s bits were set).
51 | ;the appropriate g-r-s bits.
117 asll #1,%d0 |shift g-bit to c-bit
124 | ext_grs --- extract guard, round and sticky bits
144 moveml %d2/%d3,-(%a7) |make some temp registers
148 bfextu LOCAL_HI(%a0){#24:#2},%d3 |sgl prec. g-r are 2 bits right
[all …]

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