Lines Matching +full:bit +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/pinctrl/pinconf-generic.h>
30 #include "gpio-tangier.h"
46 * struct tng_gpio_context - Context to be saved during suspend-resume
69 return priv->reg_base + reg + reg_offset * 4; in gpio_reg()
73 unsigned int reg, u8 *bit) in gpio_reg_and_bit() argument
77 u8 shift = offset % 32; in gpio_reg_and_bit() local
79 *bit = shift; in gpio_reg_and_bit()
80 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit()
86 u8 shift; in tng_gpio_get() local
88 gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); in tng_gpio_get()
90 return !!(readl(gplr) & BIT(shift)); in tng_gpio_get()
97 u8 shift; in tng_gpio_set() local
99 reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); in tng_gpio_set()
101 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_set()
103 writel(BIT(shift), reg); in tng_gpio_set()
113 u8 shift; in tng_gpio_direction_input() local
115 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); in tng_gpio_direction_input()
117 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_direction_input()
120 value &= ~BIT(shift); in tng_gpio_direction_input()
131 u8 shift; in tng_gpio_direction_output() local
133 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); in tng_gpio_direction_output()
136 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_direction_output()
139 value |= BIT(shift); in tng_gpio_direction_output()
148 u8 shift; in tng_gpio_get_direction() local
150 gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); in tng_gpio_get_direction()
152 if (readl(gpdr) & BIT(shift)) in tng_gpio_get_direction()
164 u8 shift; in tng_gpio_set_debounce() local
166 gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift); in tng_gpio_set_debounce()
168 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_set_debounce()
172 value &= ~BIT(shift); in tng_gpio_set_debounce()
174 value |= BIT(shift); in tng_gpio_set_debounce()
194 return -ENOTSUPP; in tng_gpio_set_config()
204 u8 shift; in tng_irq_ack() local
206 gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); in tng_irq_ack()
208 guard(raw_spinlock_irqsave)(&priv->lock); in tng_irq_ack()
210 writel(BIT(shift), gisr); in tng_irq_ack()
217 u8 shift; in tng_irq_unmask_mask() local
219 gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); in tng_irq_unmask_mask()
221 guard(raw_spinlock_irqsave)(&priv->lock); in tng_irq_unmask_mask()
225 value |= BIT(shift); in tng_irq_unmask_mask()
227 value &= ~BIT(shift); in tng_irq_unmask_mask()
238 gpiochip_disable_irq(&priv->chip, gpio); in tng_irq_mask()
247 gpiochip_enable_irq(&priv->chip, gpio); in tng_irq_unmask()
256 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); in tng_irq_set_type()
257 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); in tng_irq_set_type()
258 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); in tng_irq_set_type()
259 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); in tng_irq_set_type()
260 u8 shift = gpio % 32; in tng_irq_set_type() local
263 guard(raw_spinlock_irqsave)(&priv->lock); in tng_irq_set_type()
267 value |= BIT(shift); in tng_irq_set_type()
269 value &= ~BIT(shift); in tng_irq_set_type()
274 value |= BIT(shift); in tng_irq_set_type()
276 value &= ~BIT(shift); in tng_irq_set_type()
285 value |= BIT(shift); in tng_irq_set_type()
287 value &= ~BIT(shift); in tng_irq_set_type()
292 value |= BIT(shift); in tng_irq_set_type()
298 value &= ~BIT(shift); in tng_irq_set_type()
312 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr); in tng_irq_set_wake()
313 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr); in tng_irq_set_wake()
314 u8 shift = gpio % 32; in tng_irq_set_wake() local
317 dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); in tng_irq_set_wake()
319 guard(raw_spinlock_irqsave)(&priv->lock); in tng_irq_set_wake()
322 writel(BIT(shift), gwsr); in tng_irq_set_wake()
326 value |= BIT(shift); in tng_irq_set_wake()
328 value &= ~BIT(shift); in tng_irq_set_wake()
335 .name = "gpio-tangier",
355 for (base = 0; base < priv->chip.ngpio; base += 32) { in tng_irq_handler()
356 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); in tng_irq_handler()
357 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); in tng_irq_handler()
367 generic_handle_domain_irq(gc->irq.domain, base + gpio); in tng_irq_handler()
379 for (base = 0; base < priv->chip.ngpio; base += 32) { in tng_irq_init_hw()
380 /* Clear the rising-edge detect register */ in tng_irq_init_hw()
381 reg = gpio_reg(&priv->chip, base, GRER); in tng_irq_init_hw()
384 /* Clear the falling-edge detect register */ in tng_irq_init_hw()
385 reg = gpio_reg(&priv->chip, base, GFER); in tng_irq_init_hw()
399 for (i = 0; i < priv->pin_info.nranges; i++) { in tng_gpio_add_pin_ranges()
400 range = &priv->pin_info.pin_ranges[i]; in tng_gpio_add_pin_ranges()
401 ret = gpiochip_add_pin_range(&priv->chip, in tng_gpio_add_pin_ranges()
402 priv->pin_info.name, in tng_gpio_add_pin_ranges()
403 range->gpio_base, in tng_gpio_add_pin_ranges()
404 range->pin_base, in tng_gpio_add_pin_ranges()
405 range->npins); in tng_gpio_add_pin_ranges()
407 dev_err(priv->dev, "failed to add GPIO pin range\n"); in tng_gpio_add_pin_ranges()
417 const struct tng_gpio_info *info = &gpio->info; in devm_tng_gpio_probe()
418 size_t nctx = DIV_ROUND_UP(info->ngpio, 32); in devm_tng_gpio_probe()
422 gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL); in devm_tng_gpio_probe()
423 if (!gpio->ctx) in devm_tng_gpio_probe()
424 return -ENOMEM; in devm_tng_gpio_probe()
426 gpio->chip.label = dev_name(dev); in devm_tng_gpio_probe()
427 gpio->chip.parent = dev; in devm_tng_gpio_probe()
428 gpio->chip.request = gpiochip_generic_request; in devm_tng_gpio_probe()
429 gpio->chip.free = gpiochip_generic_free; in devm_tng_gpio_probe()
430 gpio->chip.direction_input = tng_gpio_direction_input; in devm_tng_gpio_probe()
431 gpio->chip.direction_output = tng_gpio_direction_output; in devm_tng_gpio_probe()
432 gpio->chip.get = tng_gpio_get; in devm_tng_gpio_probe()
433 gpio->chip.set = tng_gpio_set; in devm_tng_gpio_probe()
434 gpio->chip.get_direction = tng_gpio_get_direction; in devm_tng_gpio_probe()
435 gpio->chip.set_config = tng_gpio_set_config; in devm_tng_gpio_probe()
436 gpio->chip.base = info->base; in devm_tng_gpio_probe()
437 gpio->chip.ngpio = info->ngpio; in devm_tng_gpio_probe()
438 gpio->chip.can_sleep = false; in devm_tng_gpio_probe()
439 gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; in devm_tng_gpio_probe()
441 raw_spin_lock_init(&gpio->lock); in devm_tng_gpio_probe()
443 girq = &gpio->chip.irq; in devm_tng_gpio_probe()
445 girq->init_hw = tng_irq_init_hw; in devm_tng_gpio_probe()
446 girq->parent_handler = tng_irq_handler; in devm_tng_gpio_probe()
447 girq->num_parents = 1; in devm_tng_gpio_probe()
448 girq->parents = devm_kcalloc(dev, girq->num_parents, in devm_tng_gpio_probe()
449 sizeof(*girq->parents), GFP_KERNEL); in devm_tng_gpio_probe()
450 if (!girq->parents) in devm_tng_gpio_probe()
451 return -ENOMEM; in devm_tng_gpio_probe()
453 girq->parents[0] = gpio->irq; in devm_tng_gpio_probe()
454 girq->first = info->first; in devm_tng_gpio_probe()
455 girq->default_type = IRQ_TYPE_NONE; in devm_tng_gpio_probe()
456 girq->handler = handle_bad_irq; in devm_tng_gpio_probe()
458 ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); in devm_tng_gpio_probe()
469 struct tng_gpio_context *ctx = priv->ctx; in tng_gpio_suspend()
472 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_suspend()
474 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { in tng_gpio_suspend()
476 ctx->level = readl(gpio_reg(&priv->chip, base, GPLR)); in tng_gpio_suspend()
478 ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR)); in tng_gpio_suspend()
479 ctx->grer = readl(gpio_reg(&priv->chip, base, GRER)); in tng_gpio_suspend()
480 ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER)); in tng_gpio_suspend()
481 ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_suspend()
483 ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); in tng_gpio_suspend()
492 struct tng_gpio_context *ctx = priv->ctx; in tng_gpio_resume()
495 guard(raw_spinlock_irqsave)(&priv->lock); in tng_gpio_resume()
497 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { in tng_gpio_resume()
499 writel(ctx->level, gpio_reg(&priv->chip, base, GPSR)); in tng_gpio_resume()
501 writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR)); in tng_gpio_resume()
502 writel(ctx->grer, gpio_reg(&priv->chip, base, GRER)); in tng_gpio_resume()
503 writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER)); in tng_gpio_resume()
504 writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_resume()
506 writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); in tng_gpio_resume()