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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,da850-pupd.txt1 * Pin configuration for TI DA850/OMAP-L138/AM18x
3 These SoCs have a separate controller for setting bias (internal pullup/down).
4 Bias can only be selected for groups rather than individual pins.
8 - compatible: Must be "ti,da850-pupd"
9 - reg: Base address and length of the memory resource used by the pullup/down
17 - groups: An array of strings, each string containing the name of a pin group.
20 The pin configuration parameters use the generic pinconf bindings defined in
21 pinctrl-bindings.txt in this directory. The supported parameters are
22 bias-disable, bias-pull-up, bias-pull-down.
26 -------
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H A Dthead,th1520-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
19 PADCTRL0_APSYS -> PAD Group 3
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H A Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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H A Dbrcm,nsp-gpio.txt1 Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
29 - gpio-ranges:
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H A Dbrcm,ns2-pinmux.txt4 are some individual pins that support modifying the pinconf parameters.
8 - compatible:
9 Must be "brcm,ns2-pinmux"
11 - reg:
17 - function:
20 - groups:
23 - pins:
26 The generic properties bias-disable, bias-pull-down, bias-pull-up,
27 drive-strength, slew-rate, input-enable, input-disable are supported
31 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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H A Dactions,s500-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
16 pinctrl-bindings.txt in this directory for common binding part and usage.
20 const: actions,s500-pinctrl
24 - description: GPIO Output + GPIO Input + GPIO Data
25 - description: Multiplexing Control
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H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
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H A Dactions,s900-pinctrl.txt7 - compatible: Should be "actions,s900-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
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H A Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
21 parameters, such as pull-up, slew rate, etc.
24 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
31 const: xlnx,zynqmp-pinctrl
34 '^(.*-)?(default|gpio-grp)$':
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H A Dxlnx,versal-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
21 parameters, such as pull-up, slew rate, etc.
24 pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
28 const: xlnx,versal-pinctrl
31 '^(.*-)?(default|gpio-grp)$':
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H A Dqcom,tlmm-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 Mode Multiplexer bindings and pinconf/pinmux states for these.
23 interrupt-controller: true
25 '#interrupt-cells':
28 include/dt-bindings/interrupt-controller/irq.h
31 gpio-controller: true
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/linux/arch/arm/boot/dts/actions/
H A Dowl-s500-roseapplepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
8 /dts-v1/;
10 #include "owl-s500.dtsi"
22 stdout-path = "serial2:115200n8";
30 syspwr: regulator-5v0 {
31 compatible = "regulator-fixed";
32 regulator-name = "SYSPWR";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
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/linux/arch/arm64/boot/dts/actions/
H A Ds700-cubieboard7.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
19 stdout-path = "serial3:115200n8";
35 pinctrl-names = "default";
36 pinctrl-0 = <&i2c0_default>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&i2c1_default>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&i2c2_default>;
57 pinconf {
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H A Ds900-bubblegum-96.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "ucrobotics,bubblegum-96", "actions,s900";
12 model = "Bubblegum-96";
22 stdout-path = "serial5:115200n8";
31 vcc_3v1: vcc-3v1 {
32 compatible = "regulator-fixed";
33 regulator-name = "fixed-3.1V";
34 regulator-min-microvolt = <3100000>;
35 regulator-max-microvolt = <3100000>;
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/linux/drivers/pinctrl/
H A Dpinconf-generic.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/pinctrl/pinconf.h>
27 #include "pinconf.h"
28 #include "pinctrl-utils.h"
32 PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
33 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
34 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 config PINCONF config
26 select PINCONF
41 select PINCONF
66 will be called pinctrl-apple-gpio.
69 bool "Axis ARTPEC-6 pin controller driver"
74 This is the driver for the Axis ARTPEC-6 pin controller. This driver
75 supports pin function multiplexing as well as pin bias and drive
77 found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
86 functionality. This driver supports the pinmux, push-pull and
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/linux/drivers/pinctrl/bcm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 select PINCONF
21 tristate "Broadcom BCM2835 GPIO (with PINCONF) driver"
24 select PINCONF
36 select PINCONF
44 If compiled as module it will be called pinctrl-bcm4908.
49 select PINCONF
110 bool "Broadcom iProc GPIO (with PINCONF) driver"
113 select PINCONF
119 The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
19 stdout-path = "serial0:115200n8";
23 vph: regulator-fixed {
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H A Dqcom-apq8064-ifc6410.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/leds/common.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include "qcom-apq8064-v2.0.dtsi"
12 compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
25 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&notify_led>;
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
24 pinctrl-single,gpio-range = <
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H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
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/linux/arch/arm64/boot/dts/qcom/
H A Dapq8096-db820c.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
6 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
15 #include <dt-bindings/sound/qcom,q6afe.h>
16 #include <dt-bindings/sound/qcom,q6asm.h>
17 #include <dt-bindings/sound/qcom,wcd9335.h>
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H A Dqcs404-evb.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
19 stdout-path = "serial0";
22 vph_pwr: vph-pwr-regulator {
23 compatible = "regulator-fixed";
24 regulator-name = "vph_pwr";
25 regulator-always-on;
26 regulator-boot-on;
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H A Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
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/linux/drivers/pinctrl/realtek/
H A Dpinctrl-rtd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinconf-generic.h>
23 #include "../pinctrl-utils.h"
24 #include "pinctrl-rtd.h"
35 /* custom pinconf parameters */
41 {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0},
42 {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0},
43 {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
50 return data->info->num_groups; in rtd_pinctrl_get_groups_count()
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