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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * bcm2835, bcm2836 and bcm2837 implementations.
8 interrupt-parent = <&intc>;
11 dma: dma-controller@7e007000 { label
12 compatible = "brcm,bcm2835-dm
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H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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H A Dbcm2835.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
6 compatible = "brcm,bcm2835";
9 #address-cells = <1>;
10 #size-cells = <0>;
14 compatible = "arm,arm1176jzf-s";
16 /* Source for d/i-cache-line-size and d/i-cache-sets
18 * /h/level-one-memory-system/cache-organization?lang=en
20 * Source for d/i-cache-size
23 * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU
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H A Dbcm283x.dtsi1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
19 compatible = "brcm,bcm2835";
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H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
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H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dbrcm,bcm2835-dma.txt1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dbrcm,bcm2835-sdhost.txt1 Broadcom BCM2835 SDHOST controller
4 by mmc.txt and the properties that represent the BCM2835 controller.
7 - compatible: Should be "brcm,bcm2835-sdhost".
8 - clocks: The clock feeding the SDHOST controller.
11 - dmas: DMA channel for read and write.
12 See Documentation/devicetree/bindings/dma/dma.txt for details
17 compatible = "brcm,bcm2835-sdhost";
21 dmas = <&dma 13>;
22 dma-names = "rx-tx";
H A Dbrcm,bcm2835-sdhost.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,bcm2835-sdhost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM2835 SDHOST controller
10 - Stefan Wahren <stefan.wahren@i2se.com>
13 - $ref: mmc-controller.yaml
17 const: brcm,bcm2835-sdhost
31 dma-names:
32 const: rx-tx
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dbrcm,bcm2835-i2s.txt1 * Broadcom BCM2835 SoC I2S/PCM module
4 - compatible: "brcm,bcm2835-i2s"
5 - reg: Should contain PCM registers location and length.
6 - clocks: the (PCM) clock to use
7 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
8 - dma-names: Identifier string for each DMA request line in the dmas property.
11 One of the DMA channels will be responsible for transmission (should be
17 compatible = "brcm,bcm2835-i2s";
21 dmas = <&dma 2>,
22 <&dma 3>;
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dbrcm,bcm-vc4.txt8 - compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
11 - compatible: Should be one of "brcm,bcm2835-pixelvalve0",
12 "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2"
13 - reg: Physical base address and length of the PV's registers
14 - interrupts: The interrupt number
15 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
18 - compatible: Should be "brcm,bcm2835-hvs"
19 - reg: Physical base address and length of the HVS's registers
20 - interrupts: The interrupt number
21 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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H A Dbrcm,bcm2835-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
14 const: brcm,bcm2835-hdmi
18 - description: HDMI register range
19 - description: HD register range
26 - description: The pixel clock
27 - description: The HDMI state machine clock
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-i
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
60 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
62 #include <arm/broadcom/bcm2835/bcm2835_clkman.h>
64 #include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
71 * NUM_DMA_SEGS is the number of DMA segments we want to accommodate on average.
78 ((((NUM_DMA_SEGS * BCM_SDHCI_BUFFER_SIZE) - 1) / PAGE_SIZE) + 1)
83 ((slot)->curcmd->data->len - (slot)->offset)
95 TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug);
97 &bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level");
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H A Dbcm2835_mbox.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 #include <arm/broadcom/bcm2835/bcm2835_firmware.h>
44 #include <arm/broadcom/bcm2835/bcm2835_mbox.h>
45 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
46 #include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
65 mtx_lock(&(sc)->lock); \
69 mtx_unlock(&(sc)->lock); \
91 bus_space_read_4((sc)->bst, (sc)->bsh, reg)
93 bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
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H A Dbcm2835_dma.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
112 /* DMA Control Block - 256bit aligned (p.40) */
129 /* DMA channel private info */
154 {"broadcom,bcm2835-dma", 1},
155 {"brcm,bcm2835-dma", 1},
183 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
187 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); in bcm_dma_reset()
191 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); in bcm_dma_reset()
192 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); in bcm_dma_reset()
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H A Dbcm2835_vcbus.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * mappings for use in DMA/mailbox interactions. This is only used for the
32 * arm64 SoC because the 32-bit SoC used the same mappings.
44 #include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
48 * ARM core addresses into vcbus addresses for use with the DMA/mailbox
55 * Peripherals are mapped further up at spots that vary per-SOC.
115 * we also capture the main-peripheral busdma restriction below.
141 .soc_compat = "raspberrypi,model-b",
147 .soc_compat = "brcm,bcm2835",
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/freebsd/sys/arm/conf/
H A DGENERIC2 # GENERIC -- Generic(ish) kernel config.
7 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
26 makeoptions CONF_CFLAGS="-march=armv7a"
38 files "../broadcom/bcm2835/files.bcm2836"
39 files "../broadcom/bcm2835/files.bcm283x"
95 device ahci # AHCI-compatible SATA controllers
129 device p2wi # Allwinner Push-Pull Two Wire
187 device axe # USB-Ethernet
188 device umass # Disks/Mass storage - Requires scbus and da
238 # DMA controller
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/freebsd/sys/contrib/vchiq/interface/vchiq_arm/
H A Dvchiq_2835_arm.c2 * Copyright (c) 2010-2012 Broadcom. All rights reserved.
13 * 3. The names of the above-listed copyright holders may not be used
51 #include <arm/broadcom/bcm2835/bcm2835_mbox.h>
52 #include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
79 /* BSD DMA */
160 err = -ENOMEM; in vchiq_platform_init()
169 vchiq_log_error(vchiq_core_log_level, "cannot load DMA map"); in vchiq_platform_init()
170 err = -ENOMEM; in vchiq_platform_init()
174 WARN_ON(((int)g_slot_mem & (PAGE_SIZE - 1)) != 0); in vchiq_platform_init()
178 err = -EINVAL; in vchiq_platform_init()
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/
H A Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
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