1*f126890aSEmmanuel Vadot#include "bcm283x.dtsi" 2*f126890aSEmmanuel Vadot#include "bcm2835-common.dtsi" 3*f126890aSEmmanuel Vadot 4*f126890aSEmmanuel Vadot/ { 5*f126890aSEmmanuel Vadot compatible = "brcm,bcm2837"; 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadot soc { 8*f126890aSEmmanuel Vadot ranges = <0x7e000000 0x3f000000 0x1000000>, 9*f126890aSEmmanuel Vadot <0x40000000 0x40000000 0x00001000>; 10*f126890aSEmmanuel Vadot dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 11*f126890aSEmmanuel Vadot 12*f126890aSEmmanuel Vadot local_intc: local_intc@40000000 { 13*f126890aSEmmanuel Vadot compatible = "brcm,bcm2836-l1-intc"; 14*f126890aSEmmanuel Vadot reg = <0x40000000 0x100>; 15*f126890aSEmmanuel Vadot interrupt-controller; 16*f126890aSEmmanuel Vadot #interrupt-cells = <2>; 17*f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 18*f126890aSEmmanuel Vadot }; 19*f126890aSEmmanuel Vadot }; 20*f126890aSEmmanuel Vadot 21*f126890aSEmmanuel Vadot arm-pmu { 22*f126890aSEmmanuel Vadot compatible = "arm,cortex-a53-pmu"; 23*f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 24*f126890aSEmmanuel Vadot interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 25*f126890aSEmmanuel Vadot }; 26*f126890aSEmmanuel Vadot 27*f126890aSEmmanuel Vadot timer { 28*f126890aSEmmanuel Vadot compatible = "arm,armv7-timer"; 29*f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 30*f126890aSEmmanuel Vadot interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 31*f126890aSEmmanuel Vadot <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 32*f126890aSEmmanuel Vadot <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 33*f126890aSEmmanuel Vadot <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 34*f126890aSEmmanuel Vadot always-on; 35*f126890aSEmmanuel Vadot }; 36*f126890aSEmmanuel Vadot 37*f126890aSEmmanuel Vadot cpus: cpus { 38*f126890aSEmmanuel Vadot #address-cells = <1>; 39*f126890aSEmmanuel Vadot #size-cells = <0>; 40*f126890aSEmmanuel Vadot enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 41*f126890aSEmmanuel Vadot 42*f126890aSEmmanuel Vadot /* Source for d/i-cache-line-size and d/i-cache-sets 43*f126890aSEmmanuel Vadot * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 44*f126890aSEmmanuel Vadot * /about-the-l1-memory-system?lang=en 45*f126890aSEmmanuel Vadot * 46*f126890aSEmmanuel Vadot * Source for d/i-cache-size 47*f126890aSEmmanuel Vadot * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 48*f126890aSEmmanuel Vadot */ 49*f126890aSEmmanuel Vadot cpu0: cpu@0 { 50*f126890aSEmmanuel Vadot device_type = "cpu"; 51*f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 52*f126890aSEmmanuel Vadot reg = <0>; 53*f126890aSEmmanuel Vadot enable-method = "spin-table"; 54*f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000d8>; 55*f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 56*f126890aSEmmanuel Vadot d-cache-line-size = <64>; 57*f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 58*f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 59*f126890aSEmmanuel Vadot i-cache-line-size = <64>; 60*f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 61*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 62*f126890aSEmmanuel Vadot }; 63*f126890aSEmmanuel Vadot 64*f126890aSEmmanuel Vadot cpu1: cpu@1 { 65*f126890aSEmmanuel Vadot device_type = "cpu"; 66*f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 67*f126890aSEmmanuel Vadot reg = <1>; 68*f126890aSEmmanuel Vadot enable-method = "spin-table"; 69*f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000e0>; 70*f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 71*f126890aSEmmanuel Vadot d-cache-line-size = <64>; 72*f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 73*f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 74*f126890aSEmmanuel Vadot i-cache-line-size = <64>; 75*f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 76*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 77*f126890aSEmmanuel Vadot }; 78*f126890aSEmmanuel Vadot 79*f126890aSEmmanuel Vadot cpu2: cpu@2 { 80*f126890aSEmmanuel Vadot device_type = "cpu"; 81*f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 82*f126890aSEmmanuel Vadot reg = <2>; 83*f126890aSEmmanuel Vadot enable-method = "spin-table"; 84*f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000e8>; 85*f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 86*f126890aSEmmanuel Vadot d-cache-line-size = <64>; 87*f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 88*f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 89*f126890aSEmmanuel Vadot i-cache-line-size = <64>; 90*f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 91*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 92*f126890aSEmmanuel Vadot }; 93*f126890aSEmmanuel Vadot 94*f126890aSEmmanuel Vadot cpu3: cpu@3 { 95*f126890aSEmmanuel Vadot device_type = "cpu"; 96*f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 97*f126890aSEmmanuel Vadot reg = <3>; 98*f126890aSEmmanuel Vadot enable-method = "spin-table"; 99*f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000f0>; 100*f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 101*f126890aSEmmanuel Vadot d-cache-line-size = <64>; 102*f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 103*f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 104*f126890aSEmmanuel Vadot i-cache-line-size = <64>; 105*f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 106*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 107*f126890aSEmmanuel Vadot }; 108*f126890aSEmmanuel Vadot 109*f126890aSEmmanuel Vadot /* Source for cache-line-size + cache-sets 110*f126890aSEmmanuel Vadot * https://developer.arm.com/documentation/ddi0500 111*f126890aSEmmanuel Vadot * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 112*f126890aSEmmanuel Vadot * Source for cache-size 113*f126890aSEmmanuel Vadot * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 114*f126890aSEmmanuel Vadot */ 115*f126890aSEmmanuel Vadot l2: l2-cache0 { 116*f126890aSEmmanuel Vadot compatible = "cache"; 117*f126890aSEmmanuel Vadot cache-unified; 118*f126890aSEmmanuel Vadot cache-size = <0x80000>; 119*f126890aSEmmanuel Vadot cache-line-size = <64>; 120*f126890aSEmmanuel Vadot cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 121*f126890aSEmmanuel Vadot cache-level = <2>; 122*f126890aSEmmanuel Vadot }; 123*f126890aSEmmanuel Vadot }; 124*f126890aSEmmanuel Vadot}; 125*f126890aSEmmanuel Vadot 126*f126890aSEmmanuel Vadot/* Make the BCM2835-style global interrupt controller be a child of the 127*f126890aSEmmanuel Vadot * CPU-local interrupt controller. 128*f126890aSEmmanuel Vadot */ 129*f126890aSEmmanuel Vadot&intc { 130*f126890aSEmmanuel Vadot compatible = "brcm,bcm2836-armctrl-ic"; 131*f126890aSEmmanuel Vadot reg = <0x7e00b200 0x200>; 132*f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 133*f126890aSEmmanuel Vadot interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 134*f126890aSEmmanuel Vadot}; 135*f126890aSEmmanuel Vadot 136*f126890aSEmmanuel Vadot&cpu_thermal { 137*f126890aSEmmanuel Vadot coefficients = <(-538) 412000>; 138*f126890aSEmmanuel Vadot}; 139*f126890aSEmmanuel Vadot 140*f126890aSEmmanuel Vadot/* enable thermal sensor with the correct compatible property set */ 141*f126890aSEmmanuel Vadot&thermal { 142*f126890aSEmmanuel Vadot compatible = "brcm,bcm2837-thermal"; 143*f126890aSEmmanuel Vadot status = "okay"; 144*f126890aSEmmanuel Vadot}; 145