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/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json8 "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
19 "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
30 "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
40 "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number o
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/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json8 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
19 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
30 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
40 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
50 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
82 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
87 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
97 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
102 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
107 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
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/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json8 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
18 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
28 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
65 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
75 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
80 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
85 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
104 …nds; Counts the number of underfill reads that are issued by the memory controller. This will gen…
123 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json8 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
18 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
28 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
65 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
75 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
80 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
85 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
104 …nds; Counts the number of underfill reads that are issued by the memory controller. This will gen…
123 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
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/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
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/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json31 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
42 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
142 …line back to DRAM. This event will generally count about the same as the number of partial writes,…
177 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
183 …escription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this chan…
188 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
193 …ublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel whil…
206 … "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
221 "PublicDescription": "Counts the number of times that the precharge all command was sent.",
225 "BriefDescription": "Number of DRAM Refreshes Issued",
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
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H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
14 the number of available GPIOs with a minimum number of additional
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
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H A Dgpio-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
73 /*--------------------------------------------------------------------------*/
83 int bank = offset / 32; in __davinci_direction() local
86 g = d->regs[bank]; in __davinci_direction()
87 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
88 temp = readl_relaxed(&g->dir); in __davinci_direction()
91 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
95 writel_relaxed(temp, &g->dir); in __davinci_direction()
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/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json31 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
42 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
142 …line back to DRAM. This event will generally count about the same as the number of partial writes,…
177 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
183 …escription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this chan…
188 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
193 …ublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel whil…
206 … "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
221 "PublicDescription": "Counts the number of times that the precharge all command was sent.",
231 …number of ECC errors detected and corrected by the iMC on this channel. This counter is only usef…
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/linux/drivers/thermal/mediatek/
H A Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
103 /* The total number of temperature sensors in the MT8173 */
106 /* The number of banks in the MT8173 */
109 /* The number of sensing points per bank */
112 /* The number of controller in the MT8173 */
119 #define MT8173_TEMP_MIN -20000
195 /* The total number of temperature sensors in the MT2701 */
198 /* The number of sensing points per bank */
201 /* The number of controller in the MT2701 */
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/linux/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
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/linux/drivers/mtd/devices/
H A Dspear_smi.c157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
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/linux/Documentation/devicetree/bindings/firmware/
H A Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
37 IRQ number GPIO bank GPIO pin within bank
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/linux/drivers/memory/
H A Djz4780-nemc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Alex Smith <alex@alex-smith.me.uk>
20 #include <linux/jz4780-nemc.h>
22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
42 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
43 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
44 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
61 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
64 * Return: The number of unique NEMC banks referred to by the specified NEMC
65 * child device. Unique here means that a device that references the same bank
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
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/linux/arch/arm/mach-omap2/
H A Dpowerdomain.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
10 * XXX This should be moved to the mach-omap2/ directory at the earliest
45 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
50 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
58 * Number of memory banks that are power-controllable. On OMAP4430, the
64 * Maximum number of clockdomains that can be associated with a powerdomain.
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/linux/drivers/bus/
H A Duniphier-system-bus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
24 #define UNIPHIER_SBC_NR_BANKS 8 /* number of banks (chip select) */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
43 dev_dbg(priv->dev, in uniphier_system_bus_add_bank()
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
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/linux/arch/powerpc/platforms/chrp/
H A Dgg2.h2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
29 #define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
30 #define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
39 #define GG2_PCI_BUSNO 0x40 /* Bus number */
40 #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
48 #define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
49 #define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
50 #define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
51 #define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
52 #define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
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/linux/drivers/iommu/
H A Dmsm_iommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
25 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
26 * context bank. The number of MIDs mapped to the same CB does not affect
33 /* Maximum number of context banks that can be present in IOMMU */
37 * struct msm_iommu_dev - a single IOMMU hardware instance
38 * ncb Number of context banks present on this IOMMU HW instance
40 * irq: Interrupt number
64 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
66 * num Index of this context bank within the hardware
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_transport.c1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
19 return data - mult; in adf_modulo()
24 if (((size - 1) & addr) != 0) in adf_check_ring_alignment()
25 return -EFAULT; in adf_check_ring_alignment()
40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
45 return -EFAULT; in adf_reserve_ring()
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_e610.c1 // SPDX-License-Identifier: GPL-2.0
13 * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should
37 * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin
48 * * - 0 - success.
49 * * - -EIO - CSR mechanism is not enabled.
50 * * - -EBUSY - CSR mechanism is busy.
51 * * - -EINVAL - buf_size is too big or
53 * * - -ETIME - Admin Command X command timeout.
54 * * - -EIO - Admin Command X invalid state of HICR register or
67 hw->aci.last_status = LIBIE_AQ_RC_OK; in ixgbe_aci_send_cmd_execute()
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/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
24 * @num_pins: number of pins in the group
38 * struct meson_pmx_func - a pinmux function
42 * @num_groups: number of groups in the function
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
78 * enum meson_pinconf_drv - value of drive-strength supported
88 * struct meson bank
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