Searched +full:axi +full:- +full:clkgen +full:- +full:2 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Analog Devices AXI clkgen pcore clock generator10 - Lars-Peter Clausen <lars@metafoo.de>11 - Michael Hennerich <michael.hennerich@analog.com>22 - adi,axi-clkgen-2.00.a23 - adi,zynqmp-axi-clkgen-2.00.a30 clock is the AXI bus clock that needs to be enabled so we can access the[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * AXI clkgen driver5 * Copyright 2012-2013 Analog Devices Inc.6 * Author: Lars-Peter Clausen <lars@metafoo.de>9 #include <linux/adi-axi-common.h>12 #include <linux/clk-provider.h>76 case 2: in axi_clkgen_lookup_filter()151 d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()152 d_max = min(fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()155 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()[all …]
1 # SPDX-License-Identifier: GPL-2.037 tristate "Clock driver for WM831x/2x PMICs"40 Supports the clocking subsystem of the WM831x/2x series of59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.91 tristate "Raspberry Pi RP1-based clock support"96 This multi-function device has 3 main PLLs and several clock97 generators to drive the internal sub-peripherals.106 multi-function device has one fixed-rate oscillator, clocked137 be pre-programmed to support other configurations and features not yet[all …]