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/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
74 /* Axi DMA Register definitions */
145 /* Axi Ethernet registers definition */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
185 /* Bit Masks for Axi Ethernet RAF register */
204 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
[all …]
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
11 #include <asm/asm-offsets.h>
33 * --------------------- in axs10x_enable_gpio_intc_wire()
34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
35 * --------------------- in axs10x_enable_gpio_intc_wire()
37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
39 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
43 * ------------------------ in axs10x_enable_gpio_intc_wire()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
[all …]
/linux/sound/soc/adi/
H A Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
102 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_hw_params()
112 snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL); in axi_spdif_dai_probe()
[all …]
H A Daxi-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
63 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_trigger()
80 return -EINVAL; in axi_i2s_trigger()
83 regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); in axi_i2s_trigger()
97 word_size = AXI_I2S_BITS_PER_FRAME / 2 - 1; in axi_i2s_hw_params()
98 bclk_div = DIV_ROUND_UP(clk_get_rate(i2s->clk_ref), bclk_rate) / 2 - 1; in axi_i2s_hw_params()
100 regmap_write(i2s->regmap, AXI_I2S_REG_CLK_CTRL, (word_size << 16) | in axi_i2s_hw_params()
113 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) in axi_i2s_startup()
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/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
42 void __iomem *base; member
48 void __iomem *base; member
61 void __iomem *base; member
120 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
121 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
159 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
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/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
117 (((aperture) - 2) << ((bar) * 8))
145 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
150 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
158 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
185 /* Region r AXI Region Base Address Register 0 */
190 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
192 /* Region r AXI Region Base Address Register 1 */
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
19 static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac1000_dma_axi() argument
24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi()
27 if (axi->axi_lpi_en) in dwmac1000_dma_axi()
29 if (axi->axi_xit_frm) in dwmac1000_dma_axi()
33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi()
37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi()
40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi()
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/linux/drivers/clk/imx/
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
33 static const char *gpu_axi_sels[] = { "axi", "ahb", };
34 static const char *pre_axi_sels[] = { "axi", "ahb", };
35 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m",…
51 static const char *pcie_axi_sels[] = { "axi", "ahb", };
56 static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
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H A Dclk-imx6sll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
82 void __iomem *base; in imx6sll_clocks_init() local
89 clk_hw_data->num = IMX6SLL_CLK_END; in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
101 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); in imx6sll_clocks_init()
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
[all …]
H A Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
43 static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", …
64 static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dum…
131 void __iomem *base; in imx6ul_clocks_init() local
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
[all …]
/linux/drivers/clk/
H A Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AXI clkgen driver
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/adi-axi-common.h>
12 #include <linux/clk-provider.h>
64 void __iomem *base; member
151 d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
152 d_max = min(fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
155 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
[all …]
/linux/drivers/iio/dac/
H A Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI DAC IP core
6 * Copyright 2016-2024 Analog Devices Inc.
8 #include <linux/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
32 #include "ad3552r-hs.h"
39 /* Base controls */
127 guard(mutex)(&st->lock); in axi_dac_enable()
128 ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, in axi_dac_enable()
137 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, in axi_dac_enable()
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/linux/Documentation/devicetree/bindings/media/
H A Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
[all …]
/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Samsung S5P G2D - 2D Graphics Accelerator Driver
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
29 #define SRC_BASE_ADDR_REG 0x0304 /* Src Image Base Address reg */
40 #define DST_BASE_ADDR_REG 0x0404 /* Dest Image Base Address reg */
47 #define PAT_BASE_ADDR_REG 0x0500 /* Pattern Image Base Address reg */
54 #define MASK_BASE_ADDR_REG 0x0520 /* Mask Base Address reg */
/linux/drivers/pci/controller/
H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
[all …]
/linux/arch/microblaze/include/asm/
H A Dpvr.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2007 - 2011 PetaLogix
40 #define PVR2_D_OPB_MASK 0x80000000 /* or AXI */
42 #define PVR2_I_OPB_MASK 0x20000000 /* or AXI */
65 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */
66 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */
96 /* ICache base address PVR mask */
102 /* DCache base address PVR mask */
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-rst.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CCU Resets interface driver
11 #define pr_fmt(fmt) "bt1-ccu-rst: " fmt
19 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/bt1-ccu.h>
24 #include "ccu-rst.h"
48 .base = _base, \
55 .base = _base, \
61 unsigned int base; member
66 * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
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/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
59 /* CxLBAR DMA channel x linked_list base address register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
[all …]
/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
106 /* rxcs/txcs - endpoint control and status bitmasks. */
[all …]
/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
[all …]
/linux/drivers/pmdomain/imx/
H A Dimx8m-blk-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/power/imx8mm-power.h>
20 #include <dt-bindings/power/imx8mn-power.h>
21 #include <dt-bindings/power/imx8mp-power.h>
22 #include <dt-bindings/power/imx8mq-power.h>
53 * an if-statement should be used before setting and clearing this
88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; in imx8m_blk_ctrl_power_on()
89 struct imx8m_blk_ctrl *bc = domain->bc; in imx8m_blk_ctrl_power_on()
93 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
95 pm_runtime_put_noidle(bc->bus_power_dev); in imx8m_blk_ctrl_power_on()
[all …]
/linux/drivers/clk/mmp/
H A Dclk-apmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp AXI peripharal clock operation source file
20 void __iomem *base; member
32 if (apmu->lock) in clk_apmu_enable()
33 spin_lock_irqsave(apmu->lock, flags); in clk_apmu_enable()
35 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
36 writel_relaxed(data, apmu->base); in clk_apmu_enable()
38 if (apmu->lock) in clk_apmu_enable()
39 spin_unlock_irqrestore(apmu->lock, flags); in clk_apmu_enable()
50 if (apmu->lock) in clk_apmu_disable()
[all …]

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