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/linux/drivers/iio/dac/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
33 module will be called ad3552r-hs.
52 tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
56 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
70 AD5362, AD5363, AD5370, AD5371, AD5373 multi-channel
83 AD5382, AD5383, AD5384, AD5390, AD5391, AD5392 multi-channel
93 Say yes here to build support for Analog Devices AD5421 loop-powered
94 digital-to-analog converters (DAC).
126 tristate "Analog Devices AD5592R ADC/DAC driver"
138 tristate "Analog Devices AD5593R ADC/DAC driver"
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/linux/drivers/iio/adc/
H A Dxilinx-xadc-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
36 #include "xilinx-xadc.h"
74 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
88 /* AXI register definitions */
117 * overloaded by the interrupts that it soft-lockups. For this reason the driver
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H A Dad7606.c1 // SPDX-License-Identifier: GPL-2.0
3 * AD7606 SPI ADC driver
103 -128, 1, 127,
107 -512, 4, 508,
135 .name = "ad7605-4",
144 .name = "ad7606-8",
155 .name = "ad7606-6",
167 .name = "ad7606-4",
278 if (st->gpio_reset) { in ad7606_reset()
279 gpiod_set_value(st->gpio_reset, 1); in ad7606_reset()
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/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/linux/drivers/clk/
H A Dclk-npcm8xx.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
24 #include <soc/nuvoton/clock-npcm8xx.h>
43 #define PLLCON_OTDV1 GENMASK(10, 8)
168 { 10, 2, sucksel_mux_table, "serial_usb_mux", sucksel_mux_parents,
190 { NPCM8XX_CLKDIV1, 21, 5, "pre_adc", &npcm8xx_muxes[6].hw, CLK_DIVIDER_READ_ONLY, 0, -1 },
196 …{ NPCM8XX_CLKDIV1, 28, 3, "adc", &npcm8xx_pre_divs[0].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWE…
237 val = readl_relaxed(pll->pllcon); in npcm8xx_clk_pll_recalc_rate()
265 return ERR_PTR(-ENOMEM); in npcm8xx_clk_register_pll()
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H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
35 #define PLLCON_OTDV1 GENMASK(10, 8)
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx23-pinfunc.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&icoll>;
14 * pre-existing /chosen node to be available to insert the
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,arm926ej-s";
42 compatible = "simple-bus";
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
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H A Dccu-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-a100.h"
50 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
66 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
84 .hw.init = CLK_HW_INIT("pll-periph0", "dcxo24M",
101 .hw.init = CLK_HW_INIT("pll-periph1", "dcxo24M",
117 .hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M",
137 .hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
153 .hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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