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/linux/drivers/iio/adc/
H A Dadi-axi-adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
6 * Copyright 2012-2020 Analog Devices Inc.
23 #include <linux/fpga/adi-axi-common.h>
26 #include <linux/iio/buffer-dmaengine.h>
35 /* ADC controls */
48 /* ADC Channel controls */
52 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
96 guard(mutex)(&st->lock); in axi_adc_enable()
97 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # ADC drivers
10 bool "ST-Ericsson AB8500 GPADC driver"
25 tristate "Analog Devices AD4000 ADC Driver"
31 SPI analog to digital converters (ADC).
37 tristate "Analog Device AD4130 ADC Driver"
45 Say yes here to build support for Analog Devices AD4130-8 SPI analog
46 to digital converters (ADC).
52 tristate "Analog Device AD4695 ADC Driver"
59 analog to digital converters (ADC).
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H A Dxilinx-xadc-core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
36 #include "xilinx-xadc.h"
74 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
88 /* AXI register definitions */
117 * overloaded by the interrupts that it soft-lockups. For this reason the driver
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H A Dad9467.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices AD9467 SPI ADC driver
5 * Copyright 2012-2020 Analog Devices Inc.
32 * ADI High-Speed ADC common spi interface registers
33 * See Application-Note AN-877:
34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
85 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
93 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
101 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
109 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC
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/linux/drivers/iio/dac/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
26 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
40 AD5362, AD5363, AD5370, AD5371, AD5373 multi-channel
53 AD5382, AD5383, AD5384, AD5390, AD5391, AD5392 multi-channel
63 Say yes here to build support for Analog Devices AD5421 loop-powered
64 digital-to-analog convertors (DAC).
96 tristate "Analog Devices AD5592R ADC/DAC driver"
108 tristate "Analog Devices AD5593R ADC/DAC driver"
142 Say yes here to build support for Analog Devices AD9739A Digital-to
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
60 #address-cells = <1>;
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H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
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H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/arch/arc/boot/dts/
H A Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/linux/sound/soc/codecs/
H A Drt5631.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5631.c -- RT5631 ALSA Soc Audio driver
22 #include <sound/soc-dapm.h>
68 * rt5631_write_index - write index register of 2nd layer
78 * rt5631_read_index - read index register of 2nd layer
169 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
170 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95625, 375, 0);
171 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
189 ucontrol->value.integer.value[0] = rt5631->dmic_used_flag; in rt5631_dmic_get()
200 rt5631->dmic_used_flag = ucontrol->value.integer.value[0]; in rt5631_dmic_put()
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/linux/drivers/hwmon/
H A Daxi-fan-control.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/fpga/adi-axi-common.h>
11 #include <linux/hwmon-sysfs.h>
66 iowrite32(val, ctl->base + reg); in axi_iowrite()
72 return ioread32(ctl->base + reg); in axi_ioread()
77 * T = /raw * 509.3140064 / 65535) - 280.2308787
83 u32 temp = axi_ioread(attr->index, ctl); in axi_fan_control_show()
85 temp = DIV_ROUND_CLOSEST_ULL(temp * 509314ULL, 65535) - 280230; in axi_fan_control_show()
98 ret = kstrtou32(buf, 10, &temp); in axi_fan_control_store()
103 axi_iowrite(temp, attr->index, ctl); in axi_fan_control_store()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 sensors-detect script from the lm_sensors package. Read
21 <file:Documentation/hwmon/userspace-tools.rst> for details.
76 with SMpro co-processor.
278 will be called as370-hwmon.
308 AXI HDL FAN monitoring core.
311 will be called axi-fan-control
320 lm-sensors 2.10.1 for proper userspace support.
326 tristate "AMD Family 10h+ temperature sensor"
331 the AMD Family 10h and all revisions of the AMD Family 11h,
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/drivers/clk/
H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
35 #define PLLCON_OTDV1 GENMASK(10, 8)
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
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/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx23-pinfunc.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&icoll>;
14 * pre-existing /chosen node to be available to insert the
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,arm926ej-s";
42 compatible = "simple-bus";
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
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