auto\-load (full) in projects: freebsd - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:auto +full:- +full:load (Results 1 – 25 of 1023) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...41

/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A D	LoopLoadElimination.cpp	1 //===- LoopLoadElimination.cpp - Loop Load Elimination Pass ---------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file implement a loop-aware load elimination pass. 11 // It uses LoopAccessAnalysis to identify loop-carried dependences with a 14 // of the corresponding load. This makes the load dead. 17 // may-aliasing stores can't change the value in memory before it's read by the 18 // load. 20 //===----------------------------------------------------------------------===// 66 #define LLE_OPTION "loop-load-elim" [all …]
H A D	GVN.cpp	1 //===- GVN.cpp - Eliminate redundant values and loads ---------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // instructions. It also performs simple dead load elimination. 15 //===----------------------------------------------------------------------===// 105 "Number of times we we reached gvn-max-block-speculations cut-off " 108 static cl::opt<bool> GVNEnablePRE("enable-pre", cl::init(true), cl::Hidden); 109 static cl::opt<bool> GVNEnableLoadPRE("enable-load-pre", cl::init(true)); 110 static cl::opt<bool> GVNEnableLoadInLoopPRE("enable-load-in-loop-pre", 113 GVNEnableSplitBackedgeInLoadPRE("enable-split-backedge-in-load-pre", [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A D	BPFPreserveStaticOffset.cpp	1 //===------ BPFPreserveStaticOffset.cpp -----------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // TLDR: replaces llvm.preserve.static.offset + GEP + load / store 10 // with llvm.bpf.getelementptr.and.load / store 16 // using load and store instructions with static immediate offsets. 21 // kernel. During BPF program load LDX and STX instructions 42 // %y = load %x 48 // In order for cases (a) and (b) to work the sequence %x-%y above has 51 // However, several optimization passes might sink `load` instruction [all …]
H A D	BPFCheckAndAdjustIR.cpp	1 //===------------ BPFCheckAndAdjustIR.cpp - Check and Adjust IR -----------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 // - no relocation globals in PHI node. 13 // - remove __builtin_bpf_passthrough builtins. Target independent IR 15 // - remove llvm.bpf.getelementptr.and.load builtins. 16 // - remove llvm.bpf.getelementptr.and.store builtins. 17 // - for loads and stores with base addresses from non-zero address space 20 //===----------------------------------------------------------------------===// 39 #define DEBUG_TYPE "bpf-check-and-opt-ir" [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A D	InstCombineLoadStoreAlloca.cpp	1 //===- InstCombineLoadStoreAlloca.cpp -------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file implements the visit functions for load, store and alloca. 11 //===----------------------------------------------------------------------===// 35 "instcombine-max-copied-from-constant-users", cl::init(300), 41 "enable-infer-alignment-pass", cl::init(true), cl::Hidden, cl::ZeroOrMore, 46 /// isOnlyCopiedFromConstantMemory - Recursively walk the uses of a (derived) 72 const auto [Value, IsOffset] = Elem; in isOnlyCopiedFromConstantMemory() local 73 for (auto &U : Value->uses()) { in isOnlyCopiedFromConstantMemory() [all …]
H A D	InstCombinePHI.cpp	1 //===- InstCombinePHI.cpp -------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 31 MaxNumPhis("instcombine-max-num-phis", cl::init(512), 35 "Number of phi-of-insertvalue turned into insertvalue-of-phis"); 37 "Number of phi-of-extractvalue turned into extractvalue-of-phi"); 44 auto *FirstInst = cast<Instruction>(PN.getIncomingValue(0)); in PHIArgMergedDebugLoc() 45 Inst->setDebugLoc(FirstInst->getDebugLoc()); in PHIArgMergedDebugLoc() 46 // We do not expect a CallInst here, otherwise, N-way merging of DebugLoc in PHIArgMergedDebugLoc() [all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A D	InterleavedAccessPass.cpp	1 //===- InterleavedAccessPass.cpp ------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 // An interleaved load reads data from memory into several vectors, with 14 // DE-interleaving the data on a factor. An interleaved store writes several 15 // vectors to memory with RE-interleaving the data on a factor. 23 // E.g. An interleaved load (Factor = 2): 24 // %wide.vec = load <8 x i32>, <8 x i32>* %ptr 45 //===----------------------------------------------------------------------===// 77 #define DEBUG_TYPE "interleaved-access" [all …]
H A D	ExpandMemCmp.cpp	1 //===--- ExpandMemCmp.cpp - Expand memcmp() to load/stores ----------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This pass tries to expand memcmp() calls into optimally-sized loads and 12 //===----------------------------------------------------------------------===// 42 #define DEBUG_TYPE "expand-memcmp" 51 "memcmp-num-loads-per-block", cl::Hidden, cl::init(1), 56 "max-loads-per-memcmp", cl::Hidden, 60 "max-loads-per-memcmp-opt-size", cl::Hidden, 61 cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz")); [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A D	VectorCombine.cpp	1 //===------- VectorCombine.cpp - Optimize partial vector operations -------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // transforms implemented here may not fit in traditional loop-based or SLP 13 //===----------------------------------------------------------------------===// 37 #define DEBUG_TYPE "vector-combine" 52 "disable-vector-combine", cl::init(false), cl::Hidden, 56 "disable-binop-extract-shuffle", cl::init(false), cl::Hidden, 60 "vector-combine-max-scan-instrs", cl::init(30), cl::Hidden, 91 // TODO: Direct calls from the top-level "run" loop use a plain "Instruction" [all …]
H A D	VPlanSLP.cpp	1 //===- VPlanSLP.cpp - SLP Analysis based on VPlan -------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 /// Look-ahead SLP: auto-vectorization in the presence of commutative 15 //===----------------------------------------------------------------------===// 37 #define DEBUG_TYPE "vplan-slp" 39 // Number of levels to look ahead when re-ordering multi node operands. 51 return cast<VPInstruction>(V)->getUnderlyingInstr(); in addCombined() 55 Type *T = cast<VPInstruction>(V)->getUnderlyingInstr()->getType(); in addCombined() 56 assert(!T->isVectorTy() && "Only scalar types supported for now"); in addCombined() [all …]
H A D	LoadStoreVectorizer.cpp	1 //===- LoadStoreVectorizer.cpp - GPU Load & Store Vectorizer --------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // loads/stores. Although there's nothing GPU-specific in here, this pass is 18 // that immediately following our new vector load we'll need to extract out the 19 // individual elements of the load, so we can operate on them individually. 23 // usually better just to load each element individually into its own scalar 27 // "vector load" loads directly into a series of scalar registers. In effect, 36 // Some CPU architectures, such as ARM, have instructions that load into 37 // multiple scalar registers, similar to a GPU vectorized load. In theory ARM [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	AMDGPULowerKernelAttributes.cpp	1 //===-- AMDGPULowerKernelAttributes.cpp ------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 /// get_local_size-like functions. 13 //===----------------------------------------------------------------------===// 29 #define DEBUG_TYPE "amdgpu-lower-kernel-attributes" 79 auto IntrinsicId = IsV5OrAbove ? Intrinsic::amdgcn_implicitarg_ptr in getBasePtrIntrinsic() 88 Function *F = CI->getParent()->getParent(); in processUse() 90 auto MD = F->getMetadata("reqd_work_group_size"); in processUse() 91 const bool HasReqdWorkGroupSize = MD && MD->getNumOperands() == 3; in processUse() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMParallelDSP.cpp	1 //===- ARMParallelDSP.cpp - Parallel DSP Pass -----------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// Armv6 introduced instructions to perform 32-bit SIMD operations. The 12 /// DSP intrinsics, which map on these 32-bit SIMD operations. 15 //===----------------------------------------------------------------------===// 42 #define DEBUG_TYPE "arm-parallel-dsp" 47 DisableParallelDSP("disable-arm-parallel-dsp", cl::Hidden, cl::init(false), 51 NumLoadLimit("arm-parallel-dsp-load-limit", cl::Hidden, cl::init(16), 84 /// Represent a sequence of multiply-accumulate operations with the aim to [all …]
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A D	Loads.cpp	1 //===- Loads.cpp - Local load analysis ------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines simple local analyses for load instructions. 11 //===----------------------------------------------------------------------===// 31 Align BA = Base->getPointerAlignment(DL); in isAligned() 36 /// a simple load or store. 42 assert(V->getType()->isPointerTy() && "Base must be pointer"); in isDereferenceableAndAlignedPointer() 45 if (MaxDepth-- == 0) in isDereferenceableAndAlignedPointer() 57 const Value *Base = GEP->getPointerOperand(); in isDereferenceableAndAlignedPointer() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A D	NVPTXLowerArgs.cpp	1 //===-- NVPTXLowerArgs.cpp - Lower arguments ------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 // http://docs.nvidia.com/cuda/parallel-thread-execution/#state-spaces 14 // Kernel parameters are read-only and accessible only via ld.param 29 // 1. Convert non-byval pointer arguments of CUDA kernels to pointers in the 35 // %v = load float, float* %input, align 4 44 // %v = load float, float* %input3, align 4 52 // %v = load float, float addrspace(1)* %input2, align 4 74 // %b = load ptr, ptr %b_ptr [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A D	ArgumentPromotion.cpp	1 //===- ArgumentPromotion.cpp - Promote by-reference arguments -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 29 //===----------------------------------------------------------------------===// 91 /// A representative guaranteed-executed load or store instruction for use by 103 APInt APOffset(DL.getIndexTypeSizeInBits(Ptr->getType()), Offset); in createByteGEP() 109 /// DoPromotion - This method actually performs the promotion of the specified 118 FunctionType *FTy = F->getFunctionType(); in doPromotion() 121 // Attribute - Keep track of the parameter attributes for the arguments in doPromotion() 125 // Mapping from old to new argument indices. -1 for promoted or removed in doPromotion() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	SVEIntrinsicOpts.cpp	1 //===----- SVEIntrinsicOpts - SVE ACLE Intrinsics Opts --------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 // - removes unnecessary ptrue intrinsics (llvm.aarch64.sve.ptrue), e.g: 18 // - optimizes ptest intrinsics where the operands are being needlessly 21 //===----------------------------------------------------------------------===// 43 #define DEBUG_TYPE "aarch64-sve-intrinsic-opts" 64 /// Operates at the function-scope. I.e., optimizations are applied local to 98 // Find all users of this intrinsic that are calls to convert-to-svbool in isPTruePromoted() 101 for (User *User : PTrue->users()) { in isPTruePromoted() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A D	AMDGPUMemoryUtils.cpp	1 //===-- AMDGPUMemoryUtils.cpp - -------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 24 #define DEBUG_TYPE "amdgpu-memory-utils" 31 return DL.getValueOrABITypeAlignment(GV->getPointerAlignment(DL), in getAlign() 32 GV->getValueType()); in getAlign() 38 const DataLayout &DL = M->getDataLayout(); in isDynamicLDS() 39 if (GV.getType()->getPointerAddressSpace() != AMDGPUAS::LOCAL_ADDRESS) in isDynamicLDS() 45 if (GV.getType()->getPointerAddressSpace() != AMDGPUAS::LOCAL_ADDRESS) { in isLDSVariableToLower() 52 // A constant undef variable can't be written to, and any load is in isLDSVariableToLower() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonVectorCombine.cpp	1 //===-- HexagonVectorCombine.cpp ------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // that assist in vector-based optimizations. 13 //===----------------------------------------------------------------------===// 57 #define DEBUG_TYPE "hexagon-vc" 62 cl::opt<bool> DumpModule("hvc-dump-module", cl::Hidden); 63 cl::opt<bool> VAEnabled("hvc-va", cl::Hidden, cl::init(true)); // Align 64 cl::opt<bool> VIEnabled("hvc-vi", cl::Hidden, cl::init(true)); // Idioms 65 cl::opt<bool> VADoFullStores("hvc-va-full-stores", cl::Hidden); [all …]
/freebsd/contrib/llvm-project/llvm/lib/Object/
H A D	MachOObjectFile.cpp	1 //===- MachOObjectFile.cpp - Mach-O object file binding -------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 87 return malformedError("Structure read out-of-range"); in getStructOrErr() 194 if (auto CmdOrErr = getStructOrErr<MachO::load_command>(Obj, Ptr)) { in getLoadCommandInfo() 195 if (CmdOrErr->cmdsize + Ptr > Obj.getData().end()) in getLoadCommandInfo() 196 return malformedError("load command " + Twine(LoadCommandIndex) + in getLoadCommandInfo() 198 if (CmdOrErr->cmdsize < 8) in getLoadCommandInfo() 199 return malformedError("load command " + Twine(LoadCommandIndex) + in getLoadCommandInfo() [all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-rtdyld/
H A D	llvm-rtdyld.cpp	1 //===-- llvm-rtdyld.cpp - MCJIT Testing Tool ------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This is a testing tool for use with the MC-JIT LLVM components. 11 //===----------------------------------------------------------------------===// 65 "Load, link, and execute the inputs."), 67 "Load, link, and print line information for each function."), 69 "Load, link, and print line information for each function " 72 "Like -printlineinfo but does not load the object first"), 74 "Load, link and verify the resulting memory image.")), [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86LowerAMXType.cpp	1 //===- Target/X86/X86LowerAMXType.cpp - -------------------------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 /// \file Pass to transform <256 x i32> load/store 14 /// load/store <256 x i32> instruction to AMX load/store. If the bitcast can 15 /// not be combined with load/store, we transform the bitcast to amx load/store 16 /// and <256 x i32> store/load. 18 /// If Front End not use O0 but the Mid/Back end use O0, (e.g. "Clang -O2 -S 19 /// -emit-llvm t.c" + "llc t.ll") we should make sure the amx data is volatile, 25 /// ---------------------------------------------------------- [all …]
H A D	X86SpeculativeLoadHardening.cpp	1 //====- X86SpeculativeLoadHardening.cpp - A Spectre v1 mitigation ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 /// or other condition) to reach a load with invalid inputs and leak the data 13 /// accessed by that load using a side channel out of the speculative domain. 17 /// https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html 20 //===----------------------------------------------------------------------===// 63 #define PASS_KEY "x86-slh" 71 "Number of post-load register values hardened"); 78 "x86-speculative-load-hardening", [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A D	PromoteMemoryToRegister.cpp	1 //===- PromoteMemoryToRegister.cpp - Convert allocas to registers ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 // traversing the function in depth-first order to rewrite loads and stores as 15 //===----------------------------------------------------------------------===// 66 // Only allow direct and non-volatile loads and stores... in isAllocaPromotable() 67 for (const User *U : AI->users()) { in isAllocaPromotable() 71 if (LI->isVolatile() \|\| LI->getType() != AI->getAllocatedType()) in isAllocaPromotable() 74 if (SI->getValueOperand() == AI \|\| in isAllocaPromotable() 75 SI->getValueOperand()->getType() != AI->getAllocatedType()) in isAllocaPromotable() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A D	SystemZISelDAGToDAG.cpp	1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 23 #define DEBUG_TYPE "systemz-isel" 24 #define PASS_NAME "SystemZ DAG->DAG Pattern Instruction Selection" 34 // base+displacement+index for load and store operands 37 // base+displacement+index for load address operands 47 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it. 79 Base.getNode()->dump(DAG); in dump() [all …]

12 3 4 5 6 7 8 9 10 >>...41