| /linux/drivers/pci/ |
| H A D | ats.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/pci-ats.h>
31 dev->ats_cap = pos; in pci_ats_init()
35 * pci_ats_supported - check if the device can use ATS
38 * Returns true if the device supports ATS and is allowed to use it, false
43 if (!dev->ats_cap) in pci_ats_supported()
46 return (dev->untrusted == 0); in pci_ats_supported()
51 * pci_prepare_ats - Setup the PS for ATS
56 * ensure that the VF can have ATS enabled.
65 return -EINVAL; in pci_prepare_ats()
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| /linux/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3-iommufd.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include "arm-smmu-v3.h"
19 return ERR_PTR(-ENOMEM); in arm_smmu_hw_info()
21 base_idr = master->smmu->base + ARM_SMMU_IDR0; in arm_smmu_hw_info()
23 info->idr[i] = readl_relaxed(base_idr + i); in arm_smmu_hw_info()
24 info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR); in arm_smmu_hw_info()
25 info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR); in arm_smmu_hw_info()
38 target, master, nested_domain->vsmmu->s2_parent, ats_enabled); in arm_smmu_make_nested_cd_table_ste()
40 target->data[0] = cpu_to_le64(STRTAB_STE_0_V | in arm_smmu_make_nested_cd_table_ste()
43 target->data[0] |= nested_domain->ste[0] & in arm_smmu_make_nested_cd_table_ste()
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| H A D | arm-smmu-v3.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
32 #include "arm-smmu-v3.h"
33 #include "../../dma-iommu.h"
38 "Disable MSI-based polling for CMD_SYNC completion.");
81 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
82 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
95 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
97 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
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| /linux/drivers/misc/genwqe/ |
| H A D | card_ddcb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
23 * struct ddcb - Device Driver Control Block DDCB
39 #define ASIV_LENGTH 104 /* Old specification without ATS field */
40 #define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
120 * Accessing HSI/SHI is done 32-bit wide
121 * Normally 16-bit access would work too, but on some platforms the
122 * 16 compare and swap operation is not supported. Therefore
123 * switching to 32-bit such that those platforms will work too.
151 * 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
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| H A D | card_ddcb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
26 #include <linux/dma-mapping.h>
30 #include <linux/crc-itu-t.h>
41 * +---+---+---+---+---+---+---+---+
44 * +---+---+---+---+---+---+---+---+
46 * enqueued_ddcbs = A - N = 2 - 2 = 0
49 * +---+---+---+---+---+---+---+---+
52 * +---+---+---+---+---+---+---+---+
54 * enqueued_ddcbs = N - A = 4 - 2 = 2
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| H A D | card_base.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
35 #define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */
42 #define GENWQE_DDCB_MAX 32 /* DDCBs on the work-queue */
62 #define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */
63 #define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */
67 #define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */
73 * struct genwqe_reg - Genwqe data dump functionality
82 * enum genwqe_dbg_type - Specify chip unit to dump/debug
99 #define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */
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| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwxgmac2_descs.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 unsigned int tdes3 = le32_to_cpu(p->des3); in dwxgmac2_get_tx_status()
28 unsigned int rdes3 = le32_to_cpu(p->des3); in dwxgmac2_get_rx_status()
44 return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L); in dwxgmac2_get_tx_len()
49 return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0; in dwxgmac2_get_tx_owner()
54 p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN); in dwxgmac2_set_tx_owner()
64 p->des3 |= cpu_to_le32(flags); in dwxgmac2_set_rx_owner()
69 return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0; in dwxgmac2_get_tx_ls()
74 return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL); in dwxgmac2_get_rx_frame_len()
79 p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE); in dwxgmac2_enable_tx_timestamp()
[all …]
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| H A D | hwif.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
14 int __result = -EINVAL; \
15 if ((__priv)->hw->__module && (__priv)->hw->__module->__cname) { \
16 (__priv)->hw->__module->__cname((__arg0), ##__args); \
23 int __result = -EINVAL; \
24 if ((__priv)->hw->__module && (__priv)->hw->__module->__cname) \
25 __result = (__priv)->hw->__module->__cname((__arg0), ##__args); \
85 void (*get_timestamp)(void *desc, u32 ats, u64 *ts);
87 int (*get_rx_timestamp_status)(void *desc, void *next_desc, u32 ats);
200 /* To track extra statistic (if supported) */
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| /linux/sound/soc/codecs/ |
| H A D | ak4458.c | 1 // SPDX-License-Identifier: GPL-2.0
20 #include <sound/soc-dapm.h>
84 * from -127 to 0 dB in 0.5 dB steps (mute instead of -127.5 dB)
86 static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
101 * 0, 0, 0 : Sharp Roll-Off Filter
102 * 0, 0, 1 : Slow Roll-Off Filter
103 * 0, 1, 0 : Short delay Sharp Roll-Off Filter
104 * 0, 1, 1 : Short delay Slow Roll-Off Filter
105 * 1, *, * : Super Slow Roll-Off Filter
108 "Sharp Roll-Off Filter",
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | btc_dpm.c | 1149 if ((table == NULL) || (table->count == 0)) { in btc_get_max_clock_from_voltage_dependency_table()
1154 for (i = 0; i < table->count; i++) { in btc_get_max_clock_from_voltage_dependency_table()
1155 if (clock < table->entries[i].clk) in btc_get_max_clock_from_voltage_dependency_table()
1156 clock = table->entries[i].clk; in btc_get_max_clock_from_voltage_dependency_table()
1166 if ((table == NULL) || (table->count == 0)) in btc_apply_voltage_dependency_rules()
1169 for (i = 0; i < table->count; i++) { in btc_apply_voltage_dependency_rules()
1170 if (clock <= table->entries[i].clk) { in btc_apply_voltage_dependency_rules()
1171 if (*voltage < table->entries[i].v) in btc_apply_voltage_dependency_rules()
1172 *voltage = (u16)((table->entries[i].v < max_voltage) ? in btc_apply_voltage_dependency_rules()
1173 table->entries[i].v : max_voltage); in btc_apply_voltage_dependency_rules()
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| H A D | ni_dpm.c | 728 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps()
751 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000), in ni_calculate_leakage_for_v_and_t_formula()
752 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature))); in ni_calculate_leakage_for_v_and_t_formula()
753 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000), in ni_calculate_leakage_for_v_and_t_formula()
754 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc))); in ni_calculate_leakage_for_v_and_t_formula()
775 /* we never hit the non-gddr5 limit so disable it */ in ni_dpm_vblank_too_short()
776 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; in ni_dpm_vblank_too_short()
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
801 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
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| /linux/include/uapi/linux/ |
| H A D | iommufd.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
23 * - ENOTTY: The IOCTL number itself is not supported at all
24 * - E2BIG: The IOCTL number is supported, but the provided structure has
25 * non-zero in a part the kernel does not understand.
26 * - EOPNOTSUPP: The IOCTL number is supported, and the structure is
29 * - EINVAL: Everything about the IOCTL was understood, but a field is not
31 * - ENOENT: An ID or IOVA provided does not exist.
32 * - ENOMEM: Out of memory.
33 * - EOVERFLOW: Mathematics overflowed.
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| H A D | pci_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-t
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| /linux/drivers/iommu/ |
| H A D | of_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include "iommu-priv.h"
28 if (!of_device_is_available(iommu_spec->np)) in of_iommu_xlate()
29 return -ENODEV; in of_iommu_xlate()
31 ret = iommu_fwspec_init(dev, of_fwnode_handle(iommu_spec->np)); in of_iommu_xlate()
32 if (ret == -EPROBE_DEFER) in of_iommu_xlate()
37 ops = iommu_ops_from_fwnode(&iommu_spec->np->fwnode); in of_iommu_xlate()
38 if (!ops->of_xlate || !try_module_get(ops->owner)) in of_iommu_xlate()
39 return -ENODEV; in of_iommu_xlate()
41 ret = ops->of_xlate(dev, iommu_spec); in of_iommu_xlate()
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| /linux/drivers/iommu/intel/ |
| H A D | iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2014 Intel Corporation.
17 #include <linux/dma-direct.h>
21 #include <linux/pci-ats.h>
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
38 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
39 #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
40 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
41 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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| H A D | perfmon.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 PMU_FORMAT_ATTR(event, "config:0-27"); /* ES: Events Select */
14 PMU_FORMAT_ATTR(event_group, "config:28-31"); /* EGI: Event Group Index */
68 return (iommu_pmu->filter & _filter) ? attr->mode : 0; \
82 IOMMU_PMU_ATTR(filter_requester_id, "config1:16-31", IOMMU_PMU_FILTER_REQUESTER_ID);
83 IOMMU_PMU_ATTR(filter_domain, "config1:32-47", IOMMU_PMU_FILTER_DOMAIN);
84 IOMMU_PMU_ATTR(filter_pasid, "config2:0-21", IOMMU_PMU_FILTER_PASID);
85 IOMMU_PMU_ATTR(filter_ats, "config2:24-28", IOMMU_PMU_FILTER_ATS);
86 IOMMU_PMU_ATTR(filter_page_table, "config2:32-36", IOMMU_PMU_FILTER_PAGE_TABLE);
101 if ((iommu_pmu->filter & _filter) && iommu_pmu_en_##_name(_econfig)) { \
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| H A D | pasid.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * intel-pasid.c - PASID idr, table and entry manipulation
18 #include <linux/pci-ats.h>
23 #include "../iommu-pages.h"
36 * single-thread context.
49 return -ENODEV; in intel_pasid_alloc_table()
50 if (WARN_ON(info->pasid_table)) in intel_pasid_alloc_table()
51 return -EEXIST; in intel_pasid_alloc_table()
55 return -ENOMEM; in intel_pasid_alloc_table()
57 if (info->pasid_supported) in intel_pasid_alloc_table()
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| /linux/arch/arm64/boot/dts/arm/ |
| H A D | fvp-base-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | si_dpm.h | 330 bool supported; member
679 struct at ats[2]; member
820 …NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1];
957 bool supported; member
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| /linux/net/nfc/ |
| H A D | digital_technology.c | 1 // SPDX-License-Identifier: GPL-2.0-only
173 if (skb->len < 1) in digital_in_iso_dep_pull_sod()
174 return -EIO; in digital_in_iso_dep_pull_sod()
176 pcb = *skb->data; in digital_in_iso_dep_pull_sod()
179 /* No support fo R-block nor S-block */ in digital_in_iso_dep_pull_sod()
181 pr_err("ISO_DEP R-block and S-block not supported\n"); in digital_in_iso_dep_pull_sod()
182 return -EIO; in digital_in_iso_dep_pull_sod()
186 pr_err("DID field in ISO_DEP PCB not supported\n"); in digital_in_iso_dep_pull_sod()
187 return -EIO; in digital_in_iso_dep_pull_sod()
199 * Chaining not supported so skb->len + 1 PCB byte + 2 CRC bytes must in digital_in_iso_dep_push_sod()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_irq.c | 89 "ATS",
118 * amdgpu_irq_disable_all - disable *all* interrupts
130 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
132 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
138 if (!src || !src->funcs->set || !src->num_types) in amdgpu_irq_disable_all()
141 for (k = 0; k < src->num_types; ++k) { in amdgpu_irq_disable_all()
142 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
150 spin_unlock_irqrestore(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
154 * amdgpu_irq_handler - IRQ handler
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| /linux/drivers/nfc/st95hf/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * --------------------------------------------------------------------
5 * --------------------------------------------------------------------
26 /* supported protocols */
100 * List of top-level cmds to be used internally by the driver.
250 struct device *dev = &st95context->spicontext.spidev->dev; in st95hf_send_recv_cmd()
253 return -EINVAL; in st95hf_send_recv_cmd()
255 return -EINVAL; in st95hf_send_recv_cmd()
257 return -EINVAL; in st95hf_send_recv_cmd()
268 return -EINVAL; in st95hf_send_recv_cmd()
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| /linux/include/uapi/drm/ |
| H A D | i915_drm.h | 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
158 * enum drm_i915_gem_engine_class - uapi engine type enumeration
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| /linux/tools/include/uapi/drm/ |
| H A D | i915_drm.h | 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
158 * enum drm_i915_gem_engine_class - uapi engine type enumeration
[all …]
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