728 	struct ni_power_info *pi = rdev->pm.dpm.priv;  in ni_get_pi()
735 	struct ni_ps *ps = rps->ps_priv;  in ni_get_ps()
751 	kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000),  in ni_calculate_leakage_for_v_and_t_formula()
752 			  drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature)));  in ni_calculate_leakage_for_v_and_t_formula()
753 	kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000),  in ni_calculate_leakage_for_v_and_t_formula()
754 			  drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));  in ni_calculate_leakage_for_v_and_t_formula()
775 	/* we never hit the non-gddr5 limit so disable it */  in ni_dpm_vblank_too_short()
776 	u32 switch_limit = pi->mem_gddr5 ? 450 : 0;  in ni_dpm_vblank_too_short()
795 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in ni_apply_state_adjust_rules()
801 	if (rdev->pm.dpm.ac_power)  in ni_apply_state_adjust_rules()
802 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_apply_state_adjust_rules()
804 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ni_apply_state_adjust_rules()
806 	if (rdev->pm.dpm.ac_power == false) {  in ni_apply_state_adjust_rules()
807 		for (i = 0; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
808 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ni_apply_state_adjust_rules()
809 				ps->performance_levels[i].mclk = max_limits->mclk;  in ni_apply_state_adjust_rules()
810 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ni_apply_state_adjust_rules()
811 				ps->performance_levels[i].sclk = max_limits->sclk;  in ni_apply_state_adjust_rules()
812 			if (ps->performance_levels[i].vddc > max_limits->vddc)  in ni_apply_state_adjust_rules()
813 				ps->performance_levels[i].vddc = max_limits->vddc;  in ni_apply_state_adjust_rules()
814 			if (ps->performance_levels[i].vddci > max_limits->vddci)  in ni_apply_state_adjust_rules()
815 				ps->performance_levels[i].vddci = max_limits->vddci;  in ni_apply_state_adjust_rules()
823 		ps->performance_levels[0].mclk =  in ni_apply_state_adjust_rules()
824 			ps->performance_levels[ps->performance_level_count - 1].mclk;  in ni_apply_state_adjust_rules()
825 		ps->performance_levels[0].vddci =  in ni_apply_state_adjust_rules()
826 			ps->performance_levels[ps->performance_level_count - 1].vddci;  in ni_apply_state_adjust_rules()
829 	btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,  in ni_apply_state_adjust_rules()
830 				  &ps->performance_levels[0].sclk,  in ni_apply_state_adjust_rules()
831 				  &ps->performance_levels[0].mclk);  in ni_apply_state_adjust_rules()
833 	for (i = 1; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
834 		if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)  in ni_apply_state_adjust_rules()
835 			ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;  in ni_apply_state_adjust_rules()
836 		if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)  in ni_apply_state_adjust_rules()
837 			ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;  in ni_apply_state_adjust_rules()
842 		mclk = ps->performance_levels[0].mclk;  in ni_apply_state_adjust_rules()
843 		vddci = ps->performance_levels[0].vddci;  in ni_apply_state_adjust_rules()
844 		for (i = 1; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
845 			if (mclk < ps->performance_levels[i].mclk)  in ni_apply_state_adjust_rules()
846 				mclk = ps->performance_levels[i].mclk;  in ni_apply_state_adjust_rules()
847 			if (vddci < ps->performance_levels[i].vddci)  in ni_apply_state_adjust_rules()
848 				vddci = ps->performance_levels[i].vddci;  in ni_apply_state_adjust_rules()
850 		for (i = 0; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
851 			ps->performance_levels[i].mclk = mclk;  in ni_apply_state_adjust_rules()
852 			ps->performance_levels[i].vddci = vddci;  in ni_apply_state_adjust_rules()
855 		for (i = 1; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
856 			if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)  in ni_apply_state_adjust_rules()
857 				ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;  in ni_apply_state_adjust_rules()
858 			if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)  in ni_apply_state_adjust_rules()
859 				ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;  in ni_apply_state_adjust_rules()
863 	for (i = 1; i < ps->performance_level_count; i++)  in ni_apply_state_adjust_rules()
864 		btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,  in ni_apply_state_adjust_rules()
865 					  &ps->performance_levels[i].sclk,  in ni_apply_state_adjust_rules()
866 					  &ps->performance_levels[i].mclk);  in ni_apply_state_adjust_rules()
868 	for (i = 0; i < ps->performance_level_count; i++)  in ni_apply_state_adjust_rules()
870 					      &ps->performance_levels[i]);  in ni_apply_state_adjust_rules()
872 	for (i = 0; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
873 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in ni_apply_state_adjust_rules()
874 						   ps->performance_levels[i].sclk,  in ni_apply_state_adjust_rules()
875 						   max_limits->vddc,  &ps->performance_levels[i].vddc);  in ni_apply_state_adjust_rules()
876 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in ni_apply_state_adjust_rules()
877 						   ps->performance_levels[i].mclk,  in ni_apply_state_adjust_rules()
878 						   max_limits->vddci, &ps->performance_levels[i].vddci);  in ni_apply_state_adjust_rules()
879 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in ni_apply_state_adjust_rules()
880 						   ps->performance_levels[i].mclk,  in ni_apply_state_adjust_rules()
881 						   max_limits->vddc,  &ps->performance_levels[i].vddc);  in ni_apply_state_adjust_rules()
882 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in ni_apply_state_adjust_rules()
883 						   rdev->clock.current_dispclk,  in ni_apply_state_adjust_rules()
884 						   max_limits->vddc,  &ps->performance_levels[i].vddc);  in ni_apply_state_adjust_rules()
887 	for (i = 0; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
889 					      max_limits->vddc, max_limits->vddci,  in ni_apply_state_adjust_rules()
890 					      &ps->performance_levels[i].vddc,  in ni_apply_state_adjust_rules()
891 					      &ps->performance_levels[i].vddci);  in ni_apply_state_adjust_rules()
894 	ps->dc_compatible = true;  in ni_apply_state_adjust_rules()
895 	for (i = 0; i < ps->performance_level_count; i++) {  in ni_apply_state_adjust_rules()
896 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in ni_apply_state_adjust_rules()
897 			ps->dc_compatible = false;  in ni_apply_state_adjust_rules()
899 		if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)  in ni_apply_state_adjust_rules()
900 			ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;  in ni_apply_state_adjust_rules()
996 		for (i = 0; i < table->count; i++) {  in ni_patch_single_dependency_table_based_on_leakage()
997 			if (0xff01 == table->entries[i].v) {  in ni_patch_single_dependency_table_based_on_leakage()
998 				if (pi->max_vddc == 0)  in ni_patch_single_dependency_table_based_on_leakage()
999 					return -EINVAL;  in ni_patch_single_dependency_table_based_on_leakage()
1000 				table->entries[i].v = pi->max_vddc;  in ni_patch_single_dependency_table_based_on_leakage()
1012 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in ni_patch_dependency_tables_based_on_leakage()
1015 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in ni_patch_dependency_tables_based_on_leakage()
1030 			0 : -EINVAL;
1046 		return -EINVAL;  in ni_restrict_performance_levels_before_switch()
1049 		0 : -EINVAL;  in ni_restrict_performance_levels_before_switch()
1057 			return -EINVAL;  in ni_dpm_force_performance_level()
1060 			return -EINVAL;  in ni_dpm_force_performance_level()
1063 			return -EINVAL;  in ni_dpm_force_performance_level()
1066 			return -EINVAL;  in ni_dpm_force_performance_level()
1069 			return -EINVAL;  in ni_dpm_force_performance_level()
1072 			return -EINVAL;  in ni_dpm_force_performance_level()
1075 	rdev->pm.dpm.forced_level = level;  in ni_dpm_force_performance_level()
1085 	for (i = 0; i < rdev->usec_timeout; i++) {  in ni_stop_smc()
1108 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1113 	pi->state_table_start = (u16)tmp;  in ni_process_firmware_header()
1118 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1123 	pi->soft_regs_start = (u16)tmp;  in ni_process_firmware_header()
1128 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1133 	eg_pi->mc_reg_table_start = (u16)tmp;  in ni_process_firmware_header()
1138 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1143 	ni_pi->fan_table_start = (u16)tmp;  in ni_process_firmware_header()
1148 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1153 	ni_pi->arb_table_start = (u16)tmp;  in ni_process_firmware_header()
1158 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1163 	ni_pi->cac_table_start = (u16)tmp;  in ni_process_firmware_header()
1168 					&tmp, pi->sram_end);  in ni_process_firmware_header()
1173 	ni_pi->spll_table_start = (u16)tmp;  in ni_process_firmware_header()
1183 	ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in ni_read_clock_registers()
1184 	ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in ni_read_clock_registers()
1185 	ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in ni_read_clock_registers()
1186 	ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in ni_read_clock_registers()
1187 	ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in ni_read_clock_registers()
1188 	ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in ni_read_clock_registers()
1189 	ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in ni_read_clock_registers()
1190 	ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);  in ni_read_clock_registers()
1191 	ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in ni_read_clock_registers()
1192 	ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);  in ni_read_clock_registers()
1193 	ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in ni_read_clock_registers()
1194 	ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in ni_read_clock_registers()
1195 	ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in ni_read_clock_registers()
1196 	ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in ni_read_clock_registers()
1204 	if (pi->gfx_clock_gating) {
1228 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in ni_program_response_times()
1229 	backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;  in ni_program_response_times()
1263 	for (i = 0; i < voltage_table->count; i++) {  in ni_populate_smc_voltage_table()
1264 		table->highSMIO[i] = 0;  in ni_populate_smc_voltage_table()
1265 		table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);  in ni_populate_smc_voltage_table()
1276 	if (eg_pi->vddc_voltage_table.count) {  in ni_populate_smc_voltage_tables()
1277 		ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);  in ni_populate_smc_voltage_tables()
1278 		table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;  in ni_populate_smc_voltage_tables()
1279 		table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =  in ni_populate_smc_voltage_tables()
1280 			cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);  in ni_populate_smc_voltage_tables()
1282 		for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {  in ni_populate_smc_voltage_tables()
1283 			if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {  in ni_populate_smc_voltage_tables()
1284 				table->maxVDDCIndexInPPTable = i;  in ni_populate_smc_voltage_tables()
1290 	if (eg_pi->vddci_voltage_table.count) {  in ni_populate_smc_voltage_tables()
1291 		ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);  in ni_populate_smc_voltage_tables()
1293 		table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;  in ni_populate_smc_voltage_tables()
1294 		table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =  in ni_populate_smc_voltage_tables()
1295 			cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);  in ni_populate_smc_voltage_tables()
1306 	for (i = 0; i < table->count; i++) {  in ni_populate_voltage_value()
1307 		if (value <= table->entries[i].value) {  in ni_populate_voltage_value()
1308 			voltage->index = (u8)i;  in ni_populate_voltage_value()
1309 			voltage->value = cpu_to_be16(table->entries[i].value);  in ni_populate_voltage_value()
1314 	if (i >= table->count)  in ni_populate_voltage_value()
1315 		return -EINVAL;  in ni_populate_voltage_value()
1327 	if (!pi->mvdd_control) {  in ni_populate_mvdd_value()
1328 		voltage->index = eg_pi->mvdd_high_index;  in ni_populate_mvdd_value()
1329 		voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);  in ni_populate_mvdd_value()
1333 	if (mclk <= pi->mvdd_split_frequency) {  in ni_populate_mvdd_value()
1334 		voltage->index = eg_pi->mvdd_low_index;  in ni_populate_mvdd_value()
1335 		voltage->value = cpu_to_be16(MVDD_LOW_VALUE);  in ni_populate_mvdd_value()
1337 		voltage->index = eg_pi->mvdd_high_index;  in ni_populate_mvdd_value()
1338 		voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);  in ni_populate_mvdd_value()
1346 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&  in ni_get_std_voltage_value()
1347 	    ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))  in ni_get_std_voltage_value()
1348 		*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in ni_get_std_voltage_value()
1350 		*std_voltage = be16_to_cpu(voltage->value);  in ni_get_std_voltage_value()
1359 	voltage->index = index;  in ni_populate_std_voltage_value()
1360 	voltage->value = cpu_to_be16(value);  in ni_populate_std_voltage_value()
1390 	if (ni_pi->enable_power_containment &&  in ni_calculate_power_boost_limit()
1391 	    ni_pi->use_power_boost_limit) {  in ni_calculate_power_boost_limit()
1397 		if (state->performance_level_count < 3)  in ni_calculate_power_boost_limit()
1400 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_calculate_power_boost_limit()
1401 						state->performance_levels[state->performance_level_count - 2].vddc,  in ni_calculate_power_boost_limit()
1410 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_calculate_power_boost_limit()
1411 						state->performance_levels[state->performance_level_count - 1].vddc,  in ni_calculate_power_boost_limit()
1438 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in ni_calculate_adjusted_tdp_limits()
1439 		return -EINVAL;  in ni_calculate_adjusted_tdp_limits()
1442 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1443 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1445 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in ni_calculate_adjusted_tdp_limits()
1446 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);  in ni_calculate_adjusted_tdp_limits()
1458 	if (ni_pi->enable_power_containment) {  in ni_populate_smc_tdp_limits()
1459 		NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable;  in ni_populate_smc_tdp_limits()
1467 			return -EINVAL;  in ni_populate_smc_tdp_limits()
1473 						       rdev->pm.dpm.tdp_adjustment,  in ni_populate_smc_tdp_limits()
1482 		smc_table->dpm2Params.TDPLimit =  in ni_populate_smc_tdp_limits()
1484 		smc_table->dpm2Params.NearTDPLimit =  in ni_populate_smc_tdp_limits()
1486 		smc_table->dpm2Params.SafePowerLimit =  in ni_populate_smc_tdp_limits()
1489 		smc_table->dpm2Params.PowerBoostLimit =  in ni_populate_smc_tdp_limits()
1493 					      (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +  in ni_populate_smc_tdp_limits()
1495 					      (u8 *)(&smc_table->dpm2Params.TDPLimit),  in ni_populate_smc_tdp_limits()
1496 					      sizeof(u32) * 4, pi->sram_end);  in ni_populate_smc_tdp_limits()
1534 		return -EINVAL;  in ni_copy_and_switch_arb_sets()
1559 		return -EINVAL;  in ni_copy_and_switch_arb_sets()
1576 	ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_init_arb_table_index()
1577 					&tmp, pi->sram_end);  in ni_init_arb_table_index()
1584 	return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_init_arb_table_index()
1585 					  tmp, pi->sram_end);  in ni_init_arb_table_index()
1600 	ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,  in ni_force_switch_to_arb_f0()
1601 					&tmp, pi->sram_end);  in ni_force_switch_to_arb_f0()
1620 	arb_regs->mc_arb_rfsh_rate =  in ni_populate_memory_timing_parameters()
1621 		(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);  in ni_populate_memory_timing_parameters()
1624 	radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);  in ni_populate_memory_timing_parameters()
1629 	arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);  in ni_populate_memory_timing_parameters()
1630 	arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);  in ni_populate_memory_timing_parameters()
1645 	for (i = 0; i < state->performance_level_count; i++) {  in ni_do_program_memory_timing_parameters()
1646 		ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);  in ni_do_program_memory_timing_parameters()
1651 					      (u16)(ni_pi->arb_table_start +  in ni_do_program_memory_timing_parameters()
1656 					      pi->sram_end);  in ni_do_program_memory_timing_parameters()
1675 	voltage->index = eg_pi->mvdd_high_index;  in ni_populate_initial_mvdd_value()
1676 	voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);  in ni_populate_initial_mvdd_value()
1690 	table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =  in ni_populate_smc_initial_state()
1691 		cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);  in ni_populate_smc_initial_state()
1692 	table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL_2 =  in ni_populate_smc_initial_state()
1693 		cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);  in ni_populate_smc_initial_state()
1694 	table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =  in ni_populate_smc_initial_state()
1695 		cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);  in ni_populate_smc_initial_state()
1696 	table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 =  in ni_populate_smc_initial_state()
1697 		cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);  in ni_populate_smc_initial_state()
1698 	table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =  in ni_populate_smc_initial_state()
1699 		cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);  in ni_populate_smc_initial_state()
1700 	table->initialState.level.mclk.vDLL_CNTL =  in ni_populate_smc_initial_state()
1701 		cpu_to_be32(ni_pi->clock_registers.dll_cntl);  in ni_populate_smc_initial_state()
1702 	table->initialState.level.mclk.vMPLL_SS =  in ni_populate_smc_initial_state()
1703 		cpu_to_be32(ni_pi->clock_registers.mpll_ss1);  in ni_populate_smc_initial_state()
1704 	table->initialState.level.mclk.vMPLL_SS2 =  in ni_populate_smc_initial_state()
1705 		cpu_to_be32(ni_pi->clock_registers.mpll_ss2);  in ni_populate_smc_initial_state()
1706 	table->initialState.level.mclk.mclk_value =  in ni_populate_smc_initial_state()
1707 		cpu_to_be32(initial_state->performance_levels[0].mclk);  in ni_populate_smc_initial_state()
1709 	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =  in ni_populate_smc_initial_state()
1710 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);  in ni_populate_smc_initial_state()
1711 	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =  in ni_populate_smc_initial_state()
1712 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);  in ni_populate_smc_initial_state()
1713 	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =  in ni_populate_smc_initial_state()
1714 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);  in ni_populate_smc_initial_state()
1715 	table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =  in ni_populate_smc_initial_state()
1716 		cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);  in ni_populate_smc_initial_state()
1717 	table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =  in ni_populate_smc_initial_state()
1718 		cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);  in ni_populate_smc_initial_state()
1719 	table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =  in ni_populate_smc_initial_state()
1720 		cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);  in ni_populate_smc_initial_state()
1721 	table->initialState.level.sclk.sclk_value =  in ni_populate_smc_initial_state()
1722 		cpu_to_be32(initial_state->performance_levels[0].sclk);  in ni_populate_smc_initial_state()
1723 	table->initialState.level.arbRefreshState =  in ni_populate_smc_initial_state()
1726 	table->initialState.level.ACIndex = 0;  in ni_populate_smc_initial_state()
1728 	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_populate_smc_initial_state()
1729 					initial_state->performance_levels[0].vddc,  in ni_populate_smc_initial_state()
1730 					&table->initialState.level.vddc);  in ni_populate_smc_initial_state()
1735 					       &table->initialState.level.vddc,  in ni_populate_smc_initial_state()
1739 						      table->initialState.level.vddc.index,  in ni_populate_smc_initial_state()
1740 						      &table->initialState.level.std_vddc);  in ni_populate_smc_initial_state()
1743 	if (eg_pi->vddci_control)  in ni_populate_smc_initial_state()
1745 					  &eg_pi->vddci_voltage_table,  in ni_populate_smc_initial_state()
1746 					  initial_state->performance_levels[0].vddci,  in ni_populate_smc_initial_state()
1747 					  &table->initialState.level.vddci);  in ni_populate_smc_initial_state()
1749 	ni_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);  in ni_populate_smc_initial_state()
1752 	table->initialState.level.aT = cpu_to_be32(reg);  in ni_populate_smc_initial_state()
1754 	table->initialState.level.bSP = cpu_to_be32(pi->dsp);  in ni_populate_smc_initial_state()
1756 	if (pi->boot_in_gen2)  in ni_populate_smc_initial_state()
1757 		table->initialState.level.gen2PCIE = 1;  in ni_populate_smc_initial_state()
1759 		table->initialState.level.gen2PCIE = 0;  in ni_populate_smc_initial_state()
1761 	if (pi->mem_gddr5) {  in ni_populate_smc_initial_state()
1762 		table->initialState.level.strobeMode =  in ni_populate_smc_initial_state()
1764 							 initial_state->performance_levels[0].mclk);  in ni_populate_smc_initial_state()
1766 		if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)  in ni_populate_smc_initial_state()
1767 			table->initialState.level.mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;  in ni_populate_smc_initial_state()
1769 			table->initialState.level.mcFlags =  0;  in ni_populate_smc_initial_state()
1772 	table->initialState.levelCount = 1;  in ni_populate_smc_initial_state()
1774 	table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;  in ni_populate_smc_initial_state()
1776 	table->initialState.level.dpm2.MaxPS = 0;  in ni_populate_smc_initial_state()
1777 	table->initialState.level.dpm2.NearTDPDec = 0;  in ni_populate_smc_initial_state()
1778 	table->initialState.level.dpm2.AboveSafeInc = 0;  in ni_populate_smc_initial_state()
1779 	table->initialState.level.dpm2.BelowSafeInc = 0;  in ni_populate_smc_initial_state()
1782 	table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);  in ni_populate_smc_initial_state()
1785 	table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);  in ni_populate_smc_initial_state()
1796 	u32 mpll_ad_func_cntl   = ni_pi->clock_registers.mpll_ad_func_cntl;  in ni_populate_smc_acpi_state()
1797 	u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;  in ni_populate_smc_acpi_state()
1798 	u32 mpll_dq_func_cntl   = ni_pi->clock_registers.mpll_dq_func_cntl;  in ni_populate_smc_acpi_state()
1799 	u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;  in ni_populate_smc_acpi_state()
1800 	u32 spll_func_cntl      = ni_pi->clock_registers.cg_spll_func_cntl;  in ni_populate_smc_acpi_state()
1801 	u32 spll_func_cntl_2    = ni_pi->clock_registers.cg_spll_func_cntl_2;  in ni_populate_smc_acpi_state()
1802 	u32 spll_func_cntl_3    = ni_pi->clock_registers.cg_spll_func_cntl_3;  in ni_populate_smc_acpi_state()
1803 	u32 spll_func_cntl_4    = ni_pi->clock_registers.cg_spll_func_cntl_4;  in ni_populate_smc_acpi_state()
1804 	u32 mclk_pwrmgt_cntl    = ni_pi->clock_registers.mclk_pwrmgt_cntl;  in ni_populate_smc_acpi_state()
1805 	u32 dll_cntl            = ni_pi->clock_registers.dll_cntl;  in ni_populate_smc_acpi_state()
1809 	table->ACPIState = table->initialState;  in ni_populate_smc_acpi_state()
1811 	table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;  in ni_populate_smc_acpi_state()
1813 	if (pi->acpi_vddc) {  in ni_populate_smc_acpi_state()
1815 						&eg_pi->vddc_voltage_table,  in ni_populate_smc_acpi_state()
1816 						pi->acpi_vddc, &table->ACPIState.level.vddc);  in ni_populate_smc_acpi_state()
1821 						       &table->ACPIState.level.vddc, &std_vddc);  in ni_populate_smc_acpi_state()
1824 							      table->ACPIState.level.vddc.index,  in ni_populate_smc_acpi_state()
1825 							      &table->ACPIState.level.std_vddc);  in ni_populate_smc_acpi_state()
1828 		if (pi->pcie_gen2) {  in ni_populate_smc_acpi_state()
1829 			if (pi->acpi_pcie_gen2)  in ni_populate_smc_acpi_state()
1830 				table->ACPIState.level.gen2PCIE = 1;  in ni_populate_smc_acpi_state()
1832 				table->ACPIState.level.gen2PCIE = 0;  in ni_populate_smc_acpi_state()
1834 			table->ACPIState.level.gen2PCIE = 0;  in ni_populate_smc_acpi_state()
1838 						&eg_pi->vddc_voltage_table,  in ni_populate_smc_acpi_state()
1839 						pi->min_vddc_in_table,  in ni_populate_smc_acpi_state()
1840 						&table->ACPIState.level.vddc);  in ni_populate_smc_acpi_state()
1845 						       &table->ACPIState.level.vddc,  in ni_populate_smc_acpi_state()
1849 							      table->ACPIState.level.vddc.index,  in ni_populate_smc_acpi_state()
1850 							      &table->ACPIState.level.std_vddc);  in ni_populate_smc_acpi_state()
1852 		table->ACPIState.level.gen2PCIE = 0;  in ni_populate_smc_acpi_state()
1855 	if (eg_pi->acpi_vddci) {  in ni_populate_smc_acpi_state()
1856 		if (eg_pi->vddci_control)  in ni_populate_smc_acpi_state()
1858 						  &eg_pi->vddci_voltage_table,  in ni_populate_smc_acpi_state()
1859 						  eg_pi->acpi_vddci,  in ni_populate_smc_acpi_state()
1860 						  &table->ACPIState.level.vddci);  in ni_populate_smc_acpi_state()
1868 	if (pi->mem_gddr5)  in ni_populate_smc_acpi_state()
1903 	table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);  in ni_populate_smc_acpi_state()
1904 	table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);  in ni_populate_smc_acpi_state()
1905 	table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);  in ni_populate_smc_acpi_state()
1906 	table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);  in ni_populate_smc_acpi_state()
1907 	table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);  in ni_populate_smc_acpi_state()
1908 	table->ACPIState.level.mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);  in ni_populate_smc_acpi_state()
1910 	table->ACPIState.level.mclk.mclk_value = 0;  in ni_populate_smc_acpi_state()
1912 	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);  in ni_populate_smc_acpi_state()
1913 	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);  in ni_populate_smc_acpi_state()
1914 	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);  in ni_populate_smc_acpi_state()
1915 	table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);  in ni_populate_smc_acpi_state()
1917 	table->ACPIState.level.sclk.sclk_value = 0;  in ni_populate_smc_acpi_state()
1919 	ni_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);  in ni_populate_smc_acpi_state()
1921 	if (eg_pi->dynamic_ac_timing)  in ni_populate_smc_acpi_state()
1922 		table->ACPIState.level.ACIndex = 1;  in ni_populate_smc_acpi_state()
1924 	table->ACPIState.level.dpm2.MaxPS = 0;  in ni_populate_smc_acpi_state()
1925 	table->ACPIState.level.dpm2.NearTDPDec = 0;  in ni_populate_smc_acpi_state()
1926 	table->ACPIState.level.dpm2.AboveSafeInc = 0;  in ni_populate_smc_acpi_state()
1927 	table->ACPIState.level.dpm2.BelowSafeInc = 0;  in ni_populate_smc_acpi_state()
1930 	table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);  in ni_populate_smc_acpi_state()
1933 	table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);  in ni_populate_smc_acpi_state()
1943 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in ni_init_smc_table()
1944 	NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;  in ni_init_smc_table()
1950 	switch (rdev->pm.int_thermal_type) {  in ni_init_smc_table()
1953 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;  in ni_init_smc_table()
1956 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;  in ni_init_smc_table()
1959 		table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;  in ni_init_smc_table()
1963 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in ni_init_smc_table()
1964 		table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;  in ni_init_smc_table()
1966 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)  in ni_init_smc_table()
1967 		table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;  in ni_init_smc_table()
1969 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in ni_init_smc_table()
1970 		table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;  in ni_init_smc_table()
1972 	if (pi->mem_gddr5)  in ni_init_smc_table()
1973 		table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;  in ni_init_smc_table()
1983 	table->driverState.flags = table->initialState.flags;  in ni_init_smc_table()
1984 	table->driverState.levelCount = table->initialState.levelCount;  in ni_init_smc_table()
1985 	table->driverState.levels[0] = table->initialState.level;  in ni_init_smc_table()
1987 	table->ULVState = table->initialState;  in ni_init_smc_table()
1994 	return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,  in ni_init_smc_table()
1995 				       sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);  in ni_init_smc_table()
2005 	u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;  in ni_calculate_sclk_params()
2006 	u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;  in ni_calculate_sclk_params()
2007 	u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;  in ni_calculate_sclk_params()
2008 	u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;  in ni_calculate_sclk_params()
2009 	u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;  in ni_calculate_sclk_params()
2010 	u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;  in ni_calculate_sclk_params()
2012 	u32 reference_clock = rdev->clock.spll.reference_freq;  in ni_calculate_sclk_params()
2040 	if (pi->sclk_ss) {  in ni_calculate_sclk_params()
2058 	sclk->sclk_value = engine_clock;  in ni_calculate_sclk_params()
2059 	sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;  in ni_calculate_sclk_params()
2060 	sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;  in ni_calculate_sclk_params()
2061 	sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;  in ni_calculate_sclk_params()
2062 	sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;  in ni_calculate_sclk_params()
2063 	sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;  in ni_calculate_sclk_params()
2064 	sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;  in ni_calculate_sclk_params()
2078 		sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);  in ni_populate_sclk_value()
2079 		sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);  in ni_populate_sclk_value()
2080 		sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);  in ni_populate_sclk_value()
2081 		sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);  in ni_populate_sclk_value()
2082 		sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);  in ni_populate_sclk_value()
2083 		sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);  in ni_populate_sclk_value()
2084 		sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);  in ni_populate_sclk_value()
2104 	if (ni_pi->spll_table_start == 0)  in ni_init_smc_spll_table()
2105 		return -EINVAL;  in ni_init_smc_spll_table()
2109 		return -ENOMEM;  in ni_init_smc_spll_table()
2126 			ret = -EINVAL;  in ni_init_smc_spll_table()
2129 			ret = -EINVAL;  in ni_init_smc_spll_table()
2132 			ret = -EINVAL;  in ni_init_smc_spll_table()
2135 			ret = -EINVAL;  in ni_init_smc_spll_table()
2142 		spll_table->freq[i] = cpu_to_be32(tmp);  in ni_init_smc_spll_table()
2146 		spll_table->ss[i] = cpu_to_be32(tmp);  in ni_init_smc_spll_table()
2152 		ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,  in ni_init_smc_spll_table()
2153 					      sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);  in ni_init_smc_spll_table()
2169 	u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;  in ni_populate_mclk_value()
2170 	u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;  in ni_populate_mclk_value()
2171 	u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;  in ni_populate_mclk_value()
2172 	u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;  in ni_populate_mclk_value()
2173 	u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;  in ni_populate_mclk_value()
2174 	u32 dll_cntl = ni_pi->clock_registers.dll_cntl;  in ni_populate_mclk_value()
2175 	u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;  in ni_populate_mclk_value()
2176 	u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;  in ni_populate_mclk_value()
2213 	if (pi->mem_gddr5) {  in ni_populate_mclk_value()
2236 	if (pi->mclk_ss) {  in ni_populate_mclk_value()
2242 			u32 reference_clock = rdev->clock.mpll.reference_freq;  in ni_populate_mclk_value()
2247 				return -EINVAL;  in ni_populate_mclk_value()
2260 	dll_speed = rv740_get_dll_speed(pi->mem_gddr5,  in ni_populate_mclk_value()
2285 	mclk->mclk_value = cpu_to_be32(memory_clock);  in ni_populate_mclk_value()
2286 	mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);  in ni_populate_mclk_value()
2287 	mclk->vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);  in ni_populate_mclk_value()
2288 	mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);  in ni_populate_mclk_value()
2289 	mclk->vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);  in ni_populate_mclk_value()
2290 	mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);  in ni_populate_mclk_value()
2291 	mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);  in ni_populate_mclk_value()
2292 	mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);  in ni_populate_mclk_value()
2293 	mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);  in ni_populate_mclk_value()
2306 	for (i = 0; i < ps->performance_level_count - 1; i++)  in ni_populate_smc_sp()
2307 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);  in ni_populate_smc_sp()
2309 	smc_state->levels[ps->performance_level_count - 1].bSP =  in ni_populate_smc_sp()
2310 		cpu_to_be32(pi->psp);  in ni_populate_smc_sp()
2325 	level->gen2PCIE = pi->pcie_gen2 ?  in ni_convert_power_level_to_smc()
2326 		((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;  in ni_convert_power_level_to_smc()
2328 	ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);  in ni_convert_power_level_to_smc()
2332 	level->mcFlags =  0;  in ni_convert_power_level_to_smc()
2333 	if (pi->mclk_stutter_mode_threshold &&  in ni_convert_power_level_to_smc()
2334 	    (pl->mclk <= pi->mclk_stutter_mode_threshold) &&  in ni_convert_power_level_to_smc()
2335 	    !eg_pi->uvd_enabled &&  in ni_convert_power_level_to_smc()
2338 		level->mcFlags |= NISLANDS_SMC_MC_STUTTER_EN;  in ni_convert_power_level_to_smc()
2340 	if (pi->mem_gddr5) {  in ni_convert_power_level_to_smc()
2341 		if (pl->mclk > pi->mclk_edc_enable_threshold)  in ni_convert_power_level_to_smc()
2342 			level->mcFlags |= NISLANDS_SMC_MC_EDC_RD_FLAG;  in ni_convert_power_level_to_smc()
2343 		if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)  in ni_convert_power_level_to_smc()
2344 			level->mcFlags |= NISLANDS_SMC_MC_EDC_WR_FLAG;  in ni_convert_power_level_to_smc()
2346 		level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);  in ni_convert_power_level_to_smc()
2348 		if (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) {  in ni_convert_power_level_to_smc()
2349 			if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=  in ni_convert_power_level_to_smc()
2356 			if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)  in ni_convert_power_level_to_smc()
2357 				level->mcFlags |= NISLANDS_SMC_MC_RTT_ENABLE;  in ni_convert_power_level_to_smc()
2360 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,  in ni_convert_power_level_to_smc()
2361 					     &level->mclk,  in ni_convert_power_level_to_smc()
2362 					     (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) != 0,  in ni_convert_power_level_to_smc()
2365 		ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);  in ni_convert_power_level_to_smc()
2370 	ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,  in ni_convert_power_level_to_smc()
2371 					pl->vddc, &level->vddc);  in ni_convert_power_level_to_smc()
2375 	ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);  in ni_convert_power_level_to_smc()
2380 				      level->vddc.index, &level->std_vddc);  in ni_convert_power_level_to_smc()
2382 	if (eg_pi->vddci_control) {  in ni_convert_power_level_to_smc()
2383 		ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,  in ni_convert_power_level_to_smc()
2384 						pl->vddci, &level->vddci);  in ni_convert_power_level_to_smc()
2389 	ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);  in ni_convert_power_level_to_smc()
2406 	if (state->performance_level_count >= 9)  in ni_populate_smc_t()
2407 		return -EINVAL;  in ni_populate_smc_t()
2409 	if (state->performance_level_count < 2) {  in ni_populate_smc_t()
2411 		smc_state->levels[0].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2415 	smc_state->levels[0].aT = cpu_to_be32(0);  in ni_populate_smc_t()
2417 	for (i = 0; i <= state->performance_level_count - 2; i++) {  in ni_populate_smc_t()
2418 		if (eg_pi->uvd_enabled)  in ni_populate_smc_t()
2420 				1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2),  in ni_populate_smc_t()
2422 				state->performance_levels[i + 1].sclk,  in ni_populate_smc_t()
2423 				state->performance_levels[i].sclk,  in ni_populate_smc_t()
2430 				state->performance_levels[i + 1].sclk,  in ni_populate_smc_t()
2431 				state->performance_levels[i].sclk,  in ni_populate_smc_t()
2436 			t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;  in ni_populate_smc_t()
2440 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;  in ni_populate_smc_t()
2441 		a_t |= CG_R(t_l * pi->bsp / 20000);  in ni_populate_smc_t()
2442 		smc_state->levels[i].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2444 		high_bsp = (i == state->performance_level_count - 2) ?  in ni_populate_smc_t()
2445 			pi->pbsp : pi->bsp;  in ni_populate_smc_t()
2448 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2471 	if (ni_pi->enable_power_containment == false)  in ni_populate_power_containment_values()
2474 	if (state->performance_level_count == 0)  in ni_populate_power_containment_values()
2475 		return -EINVAL;  in ni_populate_power_containment_values()
2477 	if (smc_state->levelCount != state->performance_level_count)  in ni_populate_power_containment_values()
2478 		return -EINVAL;  in ni_populate_power_containment_values()
2482 					       rdev->pm.dpm.tdp_adjustment,  in ni_populate_power_containment_values()
2491 					 pi->state_table_start +  in ni_populate_power_containment_values()
2495 					 pi->sram_end);  in ni_populate_power_containment_values()
2499 	smc_state->levels[0].dpm2.MaxPS = 0;  in ni_populate_power_containment_values()
2500 	smc_state->levels[0].dpm2.NearTDPDec = 0;  in ni_populate_power_containment_values()
2501 	smc_state->levels[0].dpm2.AboveSafeInc = 0;  in ni_populate_power_containment_values()
2502 	smc_state->levels[0].dpm2.BelowSafeInc = 0;  in ni_populate_power_containment_values()
2503 	smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;  in ni_populate_power_containment_values()
2505 	for (i = 1; i < state->performance_level_count; i++) {  in ni_populate_power_containment_values()
2506 		prev_sclk = state->performance_levels[i-1].sclk;  in ni_populate_power_containment_values()
2507 		max_sclk  = state->performance_levels[i].sclk;  in ni_populate_power_containment_values()
2508 		max_ps_percent = (i != (state->performance_level_count - 1)) ?  in ni_populate_power_containment_values()
2512 			return -EINVAL;  in ni_populate_power_containment_values()
2514 		if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled)  in ni_populate_power_containment_values()
2521 		if (min_sclk < state->performance_levels[0].sclk)  in ni_populate_power_containment_values()
2522 			min_sclk = state->performance_levels[0].sclk;  in ni_populate_power_containment_values()
2525 			return -EINVAL;  in ni_populate_power_containment_values()
2527 		smc_state->levels[i].dpm2.MaxPS =  in ni_populate_power_containment_values()
2528 			(u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);  in ni_populate_power_containment_values()
2529 		smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;  in ni_populate_power_containment_values()
2530 		smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;  in ni_populate_power_containment_values()
2531 		smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;  in ni_populate_power_containment_values()
2532 		smc_state->levels[i].stateFlags |=  in ni_populate_power_containment_values()
2533 			((i != (state->performance_level_count - 1)) && power_boost_limit) ?  in ni_populate_power_containment_values()
2548 	bool enable_sq_ramping = ni_pi->enable_sq_ramping;  in ni_populate_sq_ramping_values()
2551 	if (state->performance_level_count == 0)  in ni_populate_sq_ramping_values()
2552 		return -EINVAL;  in ni_populate_sq_ramping_values()
2554 	if (smc_state->levelCount != state->performance_level_count)  in ni_populate_sq_ramping_values()
2555 		return -EINVAL;  in ni_populate_sq_ramping_values()
2557 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in ni_populate_sq_ramping_values()
2558 		return -EINVAL;  in ni_populate_sq_ramping_values()
2575 	for (i = 0; i < state->performance_level_count; i++) {  in ni_populate_sq_ramping_values()
2579 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in ni_populate_sq_ramping_values()
2591 		smc_state->levels[i].SQPowerThrottle   = cpu_to_be32(sq_power_throttle);  in ni_populate_sq_ramping_values()
2592 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);  in ni_populate_sq_ramping_values()
2606 	if (ni_pi->enable_power_containment) {  in ni_enable_power_containment()
2608 			if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {  in ni_enable_power_containment()
2611 					ret = -EINVAL;  in ni_enable_power_containment()
2612 					ni_pi->pc_enabled = false;  in ni_enable_power_containment()
2614 					ni_pi->pc_enabled = true;  in ni_enable_power_containment()
2620 				ret = -EINVAL;  in ni_enable_power_containment()
2621 			ni_pi->pc_enabled = false;  in ni_enable_power_containment()
2636 	u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;  in ni_convert_power_state_to_smc()
2638 	if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))  in ni_convert_power_state_to_smc()
2639 		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;  in ni_convert_power_state_to_smc()
2641 	smc_state->levelCount = 0;  in ni_convert_power_state_to_smc()
2643 	if (state->performance_level_count > NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE)  in ni_convert_power_state_to_smc()
2644 		return -EINVAL;  in ni_convert_power_state_to_smc()
2646 	for (i = 0; i < state->performance_level_count; i++) {  in ni_convert_power_state_to_smc()
2647 		ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],  in ni_convert_power_state_to_smc()
2648 						    &smc_state->levels[i]);  in ni_convert_power_state_to_smc()
2649 		smc_state->levels[i].arbRefreshState =  in ni_convert_power_state_to_smc()
2655 		if (ni_pi->enable_power_containment)  in ni_convert_power_state_to_smc()
2656 			smc_state->levels[i].displayWatermark =  in ni_convert_power_state_to_smc()
2657 				(state->performance_levels[i].sclk < threshold) ?  in ni_convert_power_state_to_smc()
2660 			smc_state->levels[i].displayWatermark = (i < 2) ?  in ni_convert_power_state_to_smc()
2663 		if (eg_pi->dynamic_ac_timing)  in ni_convert_power_state_to_smc()
2664 			smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;  in ni_convert_power_state_to_smc()
2666 			smc_state->levels[i].ACIndex = 0;  in ni_convert_power_state_to_smc()
2668 		smc_state->levelCount++;  in ni_convert_power_state_to_smc()
2678 		ni_pi->enable_power_containment = false;  in ni_convert_power_state_to_smc()
2682 		ni_pi->enable_sq_ramping = false;  in ni_convert_power_state_to_smc()
2691 	u16 address = pi->state_table_start +  in ni_upload_sw_state()
2700 		return -ENOMEM;  in ni_upload_sw_state()
2706 	ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);  in ni_upload_sw_state()
2721 	for (i = 0, j = table->last; i < table->last; i++) {  in ni_set_mc_special_registers()
2722 		switch (table->mc_reg_address[i].s1) {  in ni_set_mc_special_registers()
2725 				return -EINVAL;  in ni_set_mc_special_registers()
2727 			table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;  in ni_set_mc_special_registers()
2728 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;  in ni_set_mc_special_registers()
2729 			for (k = 0; k < table->num_entries; k++)  in ni_set_mc_special_registers()
2730 				table->mc_reg_table_entry[k].mc_data[j] =  in ni_set_mc_special_registers()
2732 					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);  in ni_set_mc_special_registers()
2735 				return -EINVAL;  in ni_set_mc_special_registers()
2738 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;  in ni_set_mc_special_registers()
2739 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;  in ni_set_mc_special_registers()
2740 			for(k = 0; k < table->num_entries; k++) {  in ni_set_mc_special_registers()
2741 				table->mc_reg_table_entry[k].mc_data[j] =  in ni_set_mc_special_registers()
2743 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);  in ni_set_mc_special_registers()
2744 				if (!pi->mem_gddr5)  in ni_set_mc_special_registers()
2745 					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;  in ni_set_mc_special_registers()
2751 				return -EINVAL;  in ni_set_mc_special_registers()
2753 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;  in ni_set_mc_special_registers()
2754 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;  in ni_set_mc_special_registers()
2755 			for (k = 0; k < table->num_entries; k++)  in ni_set_mc_special_registers()
2756 				table->mc_reg_table_entry[k].mc_data[j] =  in ni_set_mc_special_registers()
2758 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);  in ni_set_mc_special_registers()
2766 	table->last = j;  in ni_set_mc_special_registers()
2827 	for (i = 0; i < table->last; i++) {  in ni_set_valid_flag()
2828 		for (j = 1; j < table->num_entries; j++) {  in ni_set_valid_flag()
2829 			if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {  in ni_set_valid_flag()
2830 				table->valid_flag |= 1 << i;  in ni_set_valid_flag()
2842 	for (i = 0; i < table->last; i++)  in ni_set_s0_mc_reg_index()
2843 		table->mc_reg_address[i].s0 =  in ni_set_s0_mc_reg_index()
2844 			ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?  in ni_set_s0_mc_reg_index()
2845 			address : table->mc_reg_address[i].s1;  in ni_set_s0_mc_reg_index()
2853 	if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)  in ni_copy_vbios_mc_reg_table()
2854 		return -EINVAL;  in ni_copy_vbios_mc_reg_table()
2855 	if (table->num_entries > MAX_AC_TIMING_ENTRIES)  in ni_copy_vbios_mc_reg_table()
2856 		return -EINVAL;  in ni_copy_vbios_mc_reg_table()
2858 	for (i = 0; i < table->last; i++)  in ni_copy_vbios_mc_reg_table()
2859 		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;  in ni_copy_vbios_mc_reg_table()
2860 	ni_table->last = table->last;  in ni_copy_vbios_mc_reg_table()
2862 	for (i = 0; i < table->num_entries; i++) {  in ni_copy_vbios_mc_reg_table()
2863 		ni_table->mc_reg_table_entry[i].mclk_max =  in ni_copy_vbios_mc_reg_table()
2864 			table->mc_reg_table_entry[i].mclk_max;  in ni_copy_vbios_mc_reg_table()
2865 		for (j = 0; j < table->last; j++)  in ni_copy_vbios_mc_reg_table()
2866 			ni_table->mc_reg_table_entry[i].mc_data[j] =  in ni_copy_vbios_mc_reg_table()
2867 				table->mc_reg_table_entry[i].mc_data[j];  in ni_copy_vbios_mc_reg_table()
2869 	ni_table->num_entries = table->num_entries;  in ni_copy_vbios_mc_reg_table()
2879 	struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table;  in ni_initialize_mc_reg_table()
2884 		return -ENOMEM;  in ni_initialize_mc_reg_table()
2931 	for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) {  in ni_populate_mc_reg_addresses()
2932 		if (ni_pi->mc_reg_table.valid_flag & (1 << j)) {  in ni_populate_mc_reg_addresses()
2935 			mc_reg_table->address[i].s0 =  in ni_populate_mc_reg_addresses()
2936 				cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0);  in ni_populate_mc_reg_addresses()
2937 			mc_reg_table->address[i].s1 =  in ni_populate_mc_reg_addresses()
2938 				cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1);  in ni_populate_mc_reg_addresses()
2942 	mc_reg_table->last = (u8)i;  in ni_populate_mc_reg_addresses()
2954 			data->value[i] = cpu_to_be32(entry->mc_data[j]);  in ni_convert_mc_registers()
2967 	for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) {  in ni_convert_mc_reg_table_entry_to_smc()
2968 		if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in ni_convert_mc_reg_table_entry_to_smc()
2972 	if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0))  in ni_convert_mc_reg_table_entry_to_smc()
2973 		--i;  in ni_convert_mc_reg_table_entry_to_smc()
2975 	ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i],  in ni_convert_mc_reg_table_entry_to_smc()
2977 				ni_pi->mc_reg_table.last,  in ni_convert_mc_reg_table_entry_to_smc()
2978 				ni_pi->mc_reg_table.valid_flag);  in ni_convert_mc_reg_table_entry_to_smc()
2988 	for (i = 0; i < state->performance_level_count; i++) {  in ni_convert_mc_reg_table_to_smc()
2990 						     &state->performance_levels[i],  in ni_convert_mc_reg_table_to_smc()
2991 						     &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);  in ni_convert_mc_reg_table_to_smc()
3002 	SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;  in ni_populate_mc_reg_table()
3010 	ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],  in ni_populate_mc_reg_table()
3011 					     &mc_reg_table->data[0]);  in ni_populate_mc_reg_table()
3013 	ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0],  in ni_populate_mc_reg_table()
3014 				&mc_reg_table->data[1],  in ni_populate_mc_reg_table()
3015 				ni_pi->mc_reg_table.last,  in ni_populate_mc_reg_table()
3016 				ni_pi->mc_reg_table.valid_flag);  in ni_populate_mc_reg_table()
3020 	return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,  in ni_populate_mc_reg_table()
3023 				       pi->sram_end);  in ni_populate_mc_reg_table()
3033 	SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;  in ni_upload_mc_reg_table()
3040 	address = eg_pi->mc_reg_table_start +  in ni_upload_mc_reg_table()
3044 				       (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],  in ni_upload_mc_reg_table()
3045 				       sizeof(SMC_NIslands_MCRegisterSet) * ni_new_state->performance_level_count,  in ni_upload_mc_reg_table()
3046 				       pi->sram_end);  in ni_upload_mc_reg_table()
3060 	table_size = eg_pi->vddc_voltage_table.count;  in ni_init_driver_calculated_leakage_table()
3071 			if (t < ni_pi->cac_data.leakage_minimum_temperature)  in ni_init_driver_calculated_leakage_table()
3072 				t = ni_pi->cac_data.leakage_minimum_temperature;  in ni_init_driver_calculated_leakage_table()
3075 							 &ni_pi->cac_data.leakage_coefficients,  in ni_init_driver_calculated_leakage_table()
3076 							 eg_pi->vddc_voltage_table.entries[j].value,  in ni_init_driver_calculated_leakage_table()
3078 							 ni_pi->cac_data.i_leakage,  in ni_init_driver_calculated_leakage_table()
3085 			cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(smc_leakage);  in ni_init_driver_calculated_leakage_table()
3091 			cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(max_leakage);  in ni_init_driver_calculated_leakage_table()
3101 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in ni_init_simplified_leakage_table()
3106 	table_size = leakage_table->count;  in ni_init_simplified_leakage_table()
3108 	if (eg_pi->vddc_voltage_table.count != table_size)  in ni_init_simplified_leakage_table()
3109 		table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ?  in ni_init_simplified_leakage_table()
3110 			eg_pi->vddc_voltage_table.count : leakage_table->count;  in ni_init_simplified_leakage_table()
3116 		return -EINVAL;  in ni_init_simplified_leakage_table()
3121 		smc_leakage = leakage_table->entries[j].leakage;  in ni_init_simplified_leakage_table()
3127 			cac_tables->cac_lkge_lut[i][j] =  in ni_init_simplified_leakage_table()
3133 			cac_tables->cac_lkge_lut[i][j] =  in ni_init_simplified_leakage_table()
3147 	if (ni_pi->enable_cac == false)  in ni_initialize_smc_cac_tables()
3152 		return -ENOMEM;  in ni_initialize_smc_cac_tables()
3155 	reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |  in ni_initialize_smc_cac_tables()
3156 		TID_UNIT(ni_pi->cac_weights->tid_unit));  in ni_initialize_smc_cac_tables()
3160 		ni_pi->dc_cac_table[i] = ni_pi->cac_weights->dc_cac[i];  in ni_initialize_smc_cac_tables()
3163 		cac_tables->cac_bif_lut[i] = ni_pi->cac_weights->pcie_cac[i];  in ni_initialize_smc_cac_tables()
3165 	ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;  in ni_initialize_smc_cac_tables()
3166 	ni_pi->cac_data.pwr_const = 0;  in ni_initialize_smc_cac_tables()
3167 	ni_pi->cac_data.dc_cac_value = ni_pi->dc_cac_table[NISLANDS_DCCAC_LEVEL_0];  in ni_initialize_smc_cac_tables()
3168 	ni_pi->cac_data.bif_cac_value = 0;  in ni_initialize_smc_cac_tables()
3169 	ni_pi->cac_data.mc_wr_weight = ni_pi->cac_weights->mc_write_weight;  in ni_initialize_smc_cac_tables()
3170 	ni_pi->cac_data.mc_rd_weight = ni_pi->cac_weights->mc_read_weight;  in ni_initialize_smc_cac_tables()
3171 	ni_pi->cac_data.allow_ovrflw = 0;  in ni_initialize_smc_cac_tables()
3172 	ni_pi->cac_data.l2num_win_tdp = ni_pi->lta_window_size;  in ni_initialize_smc_cac_tables()
3173 	ni_pi->cac_data.num_win_tdp = 0;  in ni_initialize_smc_cac_tables()
3174 	ni_pi->cac_data.lts_truncate_n = ni_pi->lts_truncate;  in ni_initialize_smc_cac_tables()
3176 	if (ni_pi->driver_calculate_cac_leakage)  in ni_initialize_smc_cac_tables()
3184 	cac_tables->pwr_const      = cpu_to_be32(ni_pi->cac_data.pwr_const);  in ni_initialize_smc_cac_tables()
3185 	cac_tables->dc_cacValue    = cpu_to_be32(ni_pi->cac_data.dc_cac_value);  in ni_initialize_smc_cac_tables()
3186 	cac_tables->bif_cacValue   = cpu_to_be32(ni_pi->cac_data.bif_cac_value);  in ni_initialize_smc_cac_tables()
3187 	cac_tables->AllowOvrflw    = ni_pi->cac_data.allow_ovrflw;  in ni_initialize_smc_cac_tables()
3188 	cac_tables->MCWrWeight     = ni_pi->cac_data.mc_wr_weight;  in ni_initialize_smc_cac_tables()
3189 	cac_tables->MCRdWeight     = ni_pi->cac_data.mc_rd_weight;  in ni_initialize_smc_cac_tables()
3190 	cac_tables->numWin_TDP     = ni_pi->cac_data.num_win_tdp;  in ni_initialize_smc_cac_tables()
3191 	cac_tables->l2numWin_TDP   = ni_pi->cac_data.l2num_win_tdp;  in ni_initialize_smc_cac_tables()
3192 	cac_tables->lts_truncate_n = ni_pi->cac_data.lts_truncate_n;  in ni_initialize_smc_cac_tables()
3194 	ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,  in ni_initialize_smc_cac_tables()
3195 				      sizeof(PP_NIslands_CACTABLES), pi->sram_end);  in ni_initialize_smc_cac_tables()
3199 		ni_pi->enable_cac = false;  in ni_initialize_smc_cac_tables()
3200 		ni_pi->enable_power_containment = false;  in ni_initialize_smc_cac_tables()
3213 	if (!ni_pi->enable_cac ||  in ni_initialize_hardware_cac_manager()
3214 	    !ni_pi->cac_configuration_required)  in ni_initialize_hardware_cac_manager()
3217 	if (ni_pi->cac_weights == NULL)  in ni_initialize_hardware_cac_manager()
3218 		return -EINVAL;  in ni_initialize_hardware_cac_manager()
3223 	reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |  in ni_initialize_hardware_cac_manager()
3224 		WEIGHT_TCP_SIG1(ni_pi->cac_weights->weight_tcp_sig1) |  in ni_initialize_hardware_cac_manager()
3225 		WEIGHT_TA_SIG(ni_pi->cac_weights->weight_ta_sig));  in ni_initialize_hardware_cac_manager()
3231 	reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |  in ni_initialize_hardware_cac_manager()
3232 		WEIGHT_TCC_EN1(ni_pi->cac_weights->weight_tcc_en1) |  in ni_initialize_hardware_cac_manager()
3233 		WEIGHT_TCC_EN2(ni_pi->cac_weights->weight_tcc_en2));  in ni_initialize_hardware_cac_manager()
3240 	reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |  in ni_initialize_hardware_cac_manager()
3241 		WEIGHT_CB_EN1(ni_pi->cac_weights->weight_cb_en1) |  in ni_initialize_hardware_cac_manager()
3242 		WEIGHT_CB_EN2(ni_pi->cac_weights->weight_cb_en2) |  in ni_initialize_hardware_cac_manager()
3243 		WEIGHT_CB_EN3(ni_pi->cac_weights->weight_cb_en3));  in ni_initialize_hardware_cac_manager()
3250 	reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |  in ni_initialize_hardware_cac_manager()
3251 		WEIGHT_DB_SIG1(ni_pi->cac_weights->weight_db_sig1) |  in ni_initialize_hardware_cac_manager()
3252 		WEIGHT_DB_SIG2(ni_pi->cac_weights->weight_db_sig2) |  in ni_initialize_hardware_cac_manager()
3253 		WEIGHT_DB_SIG3(ni_pi->cac_weights->weight_db_sig3));  in ni_initialize_hardware_cac_manager()
3261 	reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |  in ni_initialize_hardware_cac_manager()
3262 		WEIGHT_SXM_SIG1(ni_pi->cac_weights->weight_sxm_sig1) |  in ni_initialize_hardware_cac_manager()
3263 		WEIGHT_SXM_SIG2(ni_pi->cac_weights->weight_sxm_sig2) |  in ni_initialize_hardware_cac_manager()
3264 		WEIGHT_SXS_SIG0(ni_pi->cac_weights->weight_sxs_sig0) |  in ni_initialize_hardware_cac_manager()
3265 		WEIGHT_SXS_SIG1(ni_pi->cac_weights->weight_sxs_sig1));  in ni_initialize_hardware_cac_manager()
3272 	reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |  in ni_initialize_hardware_cac_manager()
3273 		WEIGHT_XBR_1(ni_pi->cac_weights->weight_xbr_1) |  in ni_initialize_hardware_cac_manager()
3274 		WEIGHT_XBR_2(ni_pi->cac_weights->weight_xbr_2) |  in ni_initialize_hardware_cac_manager()
3275 		WEIGHT_SPI_SIG0(ni_pi->cac_weights->weight_spi_sig0));  in ni_initialize_hardware_cac_manager()
3283 	reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |  in ni_initialize_hardware_cac_manager()
3284 		WEIGHT_SPI_SIG2(ni_pi->cac_weights->weight_spi_sig2) |  in ni_initialize_hardware_cac_manager()
3285 		WEIGHT_SPI_SIG3(ni_pi->cac_weights->weight_spi_sig3) |  in ni_initialize_hardware_cac_manager()
3286 		WEIGHT_SPI_SIG4(ni_pi->cac_weights->weight_spi_sig4) |  in ni_initialize_hardware_cac_manager()
3287 		WEIGHT_SPI_SIG5(ni_pi->cac_weights->weight_spi_sig5));  in ni_initialize_hardware_cac_manager()
3293 	reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |  in ni_initialize_hardware_cac_manager()
3294 		WEIGHT_LDS_SIG1(ni_pi->cac_weights->weight_lds_sig1) |  in ni_initialize_hardware_cac_manager()
3295 		WEIGHT_SC(ni_pi->cac_weights->weight_sc));  in ni_initialize_hardware_cac_manager()
3303 	reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |  in ni_initialize_hardware_cac_manager()
3304 		WEIGHT_CP(ni_pi->cac_weights->weight_cp) |  in ni_initialize_hardware_cac_manager()
3305 		WEIGHT_PA_SIG0(ni_pi->cac_weights->weight_pa_sig0) |  in ni_initialize_hardware_cac_manager()
3306 		WEIGHT_PA_SIG1(ni_pi->cac_weights->weight_pa_sig1) |  in ni_initialize_hardware_cac_manager()
3307 		WEIGHT_VGT_SIG0(ni_pi->cac_weights->weight_vgt_sig0));  in ni_initialize_hardware_cac_manager()
3315 	reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |  in ni_initialize_hardware_cac_manager()
3316 		WEIGHT_VGT_SIG2(ni_pi->cac_weights->weight_vgt_sig2) |  in ni_initialize_hardware_cac_manager()
3317 		WEIGHT_DC_SIG0(ni_pi->cac_weights->weight_dc_sig0) |  in ni_initialize_hardware_cac_manager()
3318 		WEIGHT_DC_SIG1(ni_pi->cac_weights->weight_dc_sig1) |  in ni_initialize_hardware_cac_manager()
3319 		WEIGHT_DC_SIG2(ni_pi->cac_weights->weight_dc_sig2));  in ni_initialize_hardware_cac_manager()
3327 	reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |  in ni_initialize_hardware_cac_manager()
3328 		WEIGHT_UVD_SIG0(ni_pi->cac_weights->weight_uvd_sig0) |  in ni_initialize_hardware_cac_manager()
3329 		WEIGHT_UVD_SIG1(ni_pi->cac_weights->weight_uvd_sig1) |  in ni_initialize_hardware_cac_manager()
3330 		WEIGHT_SPARE0(ni_pi->cac_weights->weight_spare0) |  in ni_initialize_hardware_cac_manager()
3331 		WEIGHT_SPARE1(ni_pi->cac_weights->weight_spare1));  in ni_initialize_hardware_cac_manager()
3336 	reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |  in ni_initialize_hardware_cac_manager()
3337 		WEIGHT_SQ_VSP0(ni_pi->cac_weights->weight_sq_vsp0));  in ni_initialize_hardware_cac_manager()
3341 	reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);  in ni_initialize_hardware_cac_manager()
3348 	reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |  in ni_initialize_hardware_cac_manager()
3349 		OVR_VAL_SPARE_0(ni_pi->cac_weights->ovr_val_spare_0) |  in ni_initialize_hardware_cac_manager()
3350 		OVR_MODE_SPARE_1(ni_pi->cac_weights->ovr_mode_spare_1) |  in ni_initialize_hardware_cac_manager()
3351 		OVR_VAL_SPARE_1(ni_pi->cac_weights->ovr_val_spare_1));  in ni_initialize_hardware_cac_manager()
3357 	reg |= (VSP(ni_pi->cac_weights->vsp) |  in ni_initialize_hardware_cac_manager()
3358 		VSP0(ni_pi->cac_weights->vsp0) |  in ni_initialize_hardware_cac_manager()
3359 		GPR(ni_pi->cac_weights->gpr));  in ni_initialize_hardware_cac_manager()
3369 	reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |  in ni_initialize_hardware_cac_manager()
3370 	       WRITE_WEIGHT(ni_pi->cac_weights->mc_write_weight) |  in ni_initialize_hardware_cac_manager()
3385 	if (ni_pi->enable_cac) {  in ni_enable_smc_cac()
3387 			if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {  in ni_enable_smc_cac()
3390 				if (ni_pi->support_cac_long_term_average) {  in ni_enable_smc_cac()
3393 						ni_pi->support_cac_long_term_average = false;  in ni_enable_smc_cac()
3398 					ret = -EINVAL;  in ni_enable_smc_cac()
3400 				ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false;  in ni_enable_smc_cac()
3402 		} else if (ni_pi->cac_enabled) {  in ni_enable_smc_cac()
3405 			ni_pi->cac_enabled = false;  in ni_enable_smc_cac()
3407 			if (ni_pi->support_cac_long_term_average) {  in ni_enable_smc_cac()
3410 					ni_pi->support_cac_long_term_average = false;  in ni_enable_smc_cac()
3426 		if (eg_pi->pcie_performance_request_registered == false)  in ni_pcie_performance_request()
3428 		eg_pi->pcie_performance_request_registered = true;  in ni_pcie_performance_request()
3431 		    eg_pi->pcie_performance_request_registered) {  in ni_pcie_performance_request()
3432 		eg_pi->pcie_performance_request_registered = false;  in ni_pcie_performance_request()
3448 		pi->pcie_gen2 = true;  in ni_advertise_gen2_capability()
3450 		pi->pcie_gen2 = false;  in ni_advertise_gen2_capability()
3452 	if (!pi->pcie_gen2)  in ni_advertise_gen2_capability()
3469 			if (!pi->boot_in_gen2) {  in ni_enable_bif_dynamic_pcie_gen2()
3484 			if (!pi->boot_in_gen2) {  in ni_enable_bif_dynamic_pcie_gen2()
3515 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_before_set_eng_clock()
3516 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3519 	if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=  in ni_set_uvd_clock_before_set_eng_clock()
3520 	    current_state->performance_levels[current_state->performance_level_count - 1].sclk)  in ni_set_uvd_clock_before_set_eng_clock()
3523 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3533 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_after_set_eng_clock()
3534 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3537 	if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <  in ni_set_uvd_clock_after_set_eng_clock()
3538 	    current_state->performance_levels[current_state->performance_level_count - 1].sclk)  in ni_set_uvd_clock_after_set_eng_clock()
3541 	radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
3555 	if (eg_pi->pcie_performance_request)  in ni_dpm_setup_asic()
3568 	eg_pi->current_rps = *rps;  in ni_update_current_ps()
3569 	ni_pi->current_ps = *new_ps;  in ni_update_current_ps()
3570 	eg_pi->current_rps.ps_priv = &ni_pi->current_ps;  in ni_update_current_ps()
3580 	eg_pi->requested_rps = *rps;  in ni_update_requested_ps()
3581 	ni_pi->requested_ps = *new_ps;  in ni_update_requested_ps()
3582 	eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;  in ni_update_requested_ps()
3589 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_enable()
3592 	if (pi->gfx_clock_gating)  in ni_dpm_enable()
3595 		return -EINVAL;  in ni_dpm_enable()
3596 	if (pi->mg_clock_gating)  in ni_dpm_enable()
3598 	if (eg_pi->ls_clock_gating)  in ni_dpm_enable()
3600 	if (pi->voltage_control) {  in ni_dpm_enable()
3608 	if (eg_pi->dynamic_ac_timing) {  in ni_dpm_enable()
3611 			eg_pi->dynamic_ac_timing = false;  in ni_dpm_enable()
3613 	if (pi->dynamic_ss)  in ni_dpm_enable()
3615 	if (pi->thermal_protection)  in ni_dpm_enable()
3624 	if (pi->dynamic_pcie_gen2)  in ni_dpm_enable()
3656 	if (eg_pi->dynamic_ac_timing) {  in ni_dpm_enable()
3686 	if (eg_pi->memory_transition)  in ni_dpm_enable()
3689 	if (pi->gfx_clock_gating)  in ni_dpm_enable()
3691 	if (pi->mg_clock_gating)  in ni_dpm_enable()
3693 	if (eg_pi->ls_clock_gating)  in ni_dpm_enable()
3707 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in ni_dpm_disable()
3712 	if (pi->thermal_protection)  in ni_dpm_disable()
3718 	if (pi->dynamic_pcie_gen2)  in ni_dpm_disable()
3721 	if (rdev->irq.installed &&  in ni_dpm_disable()
3722 	    r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {  in ni_dpm_disable()
3723 		rdev->irq.dpm_thermal = false;  in ni_dpm_disable()
3727 	if (pi->gfx_clock_gating)  in ni_dpm_disable()
3729 	if (pi->mg_clock_gating)  in ni_dpm_disable()
3731 	if (eg_pi->ls_clock_gating)  in ni_dpm_disable()
3743 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in ni_power_control_set_level()
3768 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in ni_dpm_pre_set_power_state()
3773 	ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);  in ni_dpm_pre_set_power_state()
3781 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_set_power_state()
3782 	struct radeon_ps *old_ps = &eg_pi->current_rps;  in ni_dpm_set_power_state()
3806 	if (eg_pi->smu_uvd_hs)  in ni_dpm_set_power_state()
3813 	if (eg_pi->dynamic_ac_timing) {  in ni_dpm_set_power_state()
3860 	struct radeon_ps *new_ps = &eg_pi->requested_rps;  in ni_dpm_post_set_power_state()
3899 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in ni_parse_pplib_non_clock_info()
3900 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in ni_parse_pplib_non_clock_info()
3901 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in ni_parse_pplib_non_clock_info()
3904 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in ni_parse_pplib_non_clock_info()
3905 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in ni_parse_pplib_non_clock_info()
3906 	} else if (r600_is_uvd_state(rps->class, rps->class2)) {  in ni_parse_pplib_non_clock_info()
3907 		rps->vclk = RV770_DEFAULT_VCLK_FREQ;  in ni_parse_pplib_non_clock_info()
3908 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in ni_parse_pplib_non_clock_info()
3910 		rps->vclk = 0;  in ni_parse_pplib_non_clock_info()
3911 		rps->dclk = 0;  in ni_parse_pplib_non_clock_info()
3914 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in ni_parse_pplib_non_clock_info()
3915 		rdev->pm.dpm.boot_ps = rps;  in ni_parse_pplib_non_clock_info()
3916 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in ni_parse_pplib_non_clock_info()
3917 		rdev->pm.dpm.uvd_ps = rps;  in ni_parse_pplib_non_clock_info()
3927 	struct rv7xx_pl *pl = &ps->performance_levels[index];  in ni_parse_pplib_clock_info()
3929 	ps->performance_level_count = index + 1;  in ni_parse_pplib_clock_info()
3931 	pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);  in ni_parse_pplib_clock_info()
3932 	pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;  in ni_parse_pplib_clock_info()
3933 	pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);  in ni_parse_pplib_clock_info()
3934 	pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;  in ni_parse_pplib_clock_info()
3936 	pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);  in ni_parse_pplib_clock_info()
3937 	pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);  in ni_parse_pplib_clock_info()
3938 	pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);  in ni_parse_pplib_clock_info()
3941 	if (pl->vddc == 0xff01) {  in ni_parse_pplib_clock_info()
3942 		if (pi->max_vddc)  in ni_parse_pplib_clock_info()
3943 			pl->vddc = pi->max_vddc;  in ni_parse_pplib_clock_info()
3946 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in ni_parse_pplib_clock_info()
3947 		pi->acpi_vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3948 		eg_pi->acpi_vddci = pl->vddci;  in ni_parse_pplib_clock_info()
3949 		if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)  in ni_parse_pplib_clock_info()
3950 			pi->acpi_pcie_gen2 = true;  in ni_parse_pplib_clock_info()
3952 			pi->acpi_pcie_gen2 = false;  in ni_parse_pplib_clock_info()
3955 	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {  in ni_parse_pplib_clock_info()
3956 		eg_pi->ulv.supported = true;  in ni_parse_pplib_clock_info()
3957 		eg_pi->ulv.pl = pl;  in ni_parse_pplib_clock_info()
3960 	if (pi->min_vddc_in_table > pl->vddc)  in ni_parse_pplib_clock_info()
3961 		pi->min_vddc_in_table = pl->vddc;  in ni_parse_pplib_clock_info()
3963 	if (pi->max_vddc_in_table < pl->vddc)  in ni_parse_pplib_clock_info()
3964 		pi->max_vddc_in_table = pl->vddc;  in ni_parse_pplib_clock_info()
3967 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in ni_parse_pplib_clock_info()
3970 		pl->mclk = rdev->clock.default_mclk;  in ni_parse_pplib_clock_info()
3971 		pl->sclk = rdev->clock.default_sclk;  in ni_parse_pplib_clock_info()
3972 		pl->vddc = vddc;  in ni_parse_pplib_clock_info()
3973 		pl->vddci = vddci;  in ni_parse_pplib_clock_info()
3976 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==  in ni_parse_pplib_clock_info()
3978 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in ni_parse_pplib_clock_info()
3979 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in ni_parse_pplib_clock_info()
3980 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in ni_parse_pplib_clock_info()
3981 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in ni_parse_pplib_clock_info()
3987 	struct radeon_mode_info *mode_info = &rdev->mode_info;  in ni_parse_power_table()
3998 	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,  in ni_parse_power_table()
4000 		return -EINVAL;  in ni_parse_power_table()
4001 	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);  in ni_parse_power_table()
4003 	rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,  in ni_parse_power_table()
4006 	if (!rdev->pm.dpm.ps)  in ni_parse_power_table()
4007 		return -ENOMEM;  in ni_parse_power_table()
4009 	for (i = 0; i < power_info->pplib.ucNumStates; i++) {  in ni_parse_power_table()
4011 			(mode_info->atom_context->bios + data_offset +  in ni_parse_power_table()
4012 			 le16_to_cpu(power_info->pplib.usStateArrayOffset) +  in ni_parse_power_table()
4013 			 i * power_info->pplib.ucStateEntrySize);  in ni_parse_power_table()
4015 			(mode_info->atom_context->bios + data_offset +  in ni_parse_power_table()
4016 			 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +  in ni_parse_power_table()
4017 			 (power_state->v1.ucNonClockStateIndex *  in ni_parse_power_table()
4018 			  power_info->pplib.ucNonClockSize));  in ni_parse_power_table()
4019 		if (power_info->pplib.ucStateEntrySize - 1) {  in ni_parse_power_table()
4023 				kfree(rdev->pm.dpm.ps);  in ni_parse_power_table()
4024 				return -ENOMEM;  in ni_parse_power_table()
4026 			rdev->pm.dpm.ps[i].ps_priv = ps;  in ni_parse_power_table()
4027 			ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in ni_parse_power_table()
4029 							 power_info->pplib.ucNonClockSize);  in ni_parse_power_table()
4030 			idx = (u8 *)&power_state->v1.ucClockStateIndices[0];  in ni_parse_power_table()
4031 			for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {  in ni_parse_power_table()
4033 					(mode_info->atom_context->bios + data_offset +  in ni_parse_power_table()
4034 					 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +  in ni_parse_power_table()
4035 					 (idx[j] * power_info->pplib.ucClockInfoSize));  in ni_parse_power_table()
4037 							  &rdev->pm.dpm.ps[i], j,  in ni_parse_power_table()
4042 	rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;  in ni_parse_power_table()
4056 		return -ENOMEM;  in ni_dpm_init()
4057 	rdev->pm.dpm.priv = ni_pi;  in ni_dpm_init()
4058 	eg_pi = &ni_pi->eg;  in ni_dpm_init()
4059 	pi = &eg_pi->rv7xx;  in ni_dpm_init()
4063 	eg_pi->ulv.supported = false;  in ni_dpm_init()
4064 	pi->acpi_vddc = 0;  in ni_dpm_init()
4065 	eg_pi->acpi_vddci = 0;  in ni_dpm_init()
4066 	pi->min_vddc_in_table = 0;  in ni_dpm_init()
4067 	pi->max_vddc_in_table = 0;  in ni_dpm_init()
4080 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in ni_dpm_init()
4084 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in ni_dpm_init()
4086 		return -ENOMEM;  in ni_dpm_init()
4088 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in ni_dpm_init()
4089 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in ni_dpm_init()
4090 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in ni_dpm_init()
4091 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in ni_dpm_init()
4092 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in ni_dpm_init()
4093 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in ni_dpm_init()
4094 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in ni_dpm_init()
4095 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in ni_dpm_init()
4096 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in ni_dpm_init()
4100 	if (rdev->pm.dpm.voltage_response_time == 0)  in ni_dpm_init()
4101 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in ni_dpm_init()
4102 	if (rdev->pm.dpm.backbias_response_time == 0)  in ni_dpm_init()
4103 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in ni_dpm_init()
4108 		pi->ref_div = dividers.ref_div + 1;  in ni_dpm_init()
4110 		pi->ref_div = R600_REFERENCEDIVIDER_DFLT;  in ni_dpm_init()
4112 	pi->rlp = RV770_RLP_DFLT;  in ni_dpm_init()
4113 	pi->rmp = RV770_RMP_DFLT;  in ni_dpm_init()
4114 	pi->lhp = RV770_LHP_DFLT;  in ni_dpm_init()
4115 	pi->lmp = RV770_LMP_DFLT;  in ni_dpm_init()
4117 	eg_pi->ats[0].rlp = RV770_RLP_DFLT;  in ni_dpm_init()
4118 	eg_pi->ats[0].rmp = RV770_RMP_DFLT;  in ni_dpm_init()
4119 	eg_pi->ats[0].lhp = RV770_LHP_DFLT;  in ni_dpm_init()
4120 	eg_pi->ats[0].lmp = RV770_LMP_DFLT;  in ni_dpm_init()
4122 	eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;  in ni_dpm_init()
4123 	eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;  in ni_dpm_init()
4124 	eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;  in ni_dpm_init()
4125 	eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;  in ni_dpm_init()
4127 	eg_pi->smu_uvd_hs = true;  in ni_dpm_init()
4129 	if (rdev->pdev->device == 0x6707) {  in ni_dpm_init()
4130 		pi->mclk_strobe_mode_threshold = 55000;  in ni_dpm_init()
4131 		pi->mclk_edc_enable_threshold = 55000;  in ni_dpm_init()
4132 		eg_pi->mclk_edc_wr_enable_threshold = 55000;  in ni_dpm_init()
4134 		pi->mclk_strobe_mode_threshold = 40000;  in ni_dpm_init()
4135 		pi->mclk_edc_enable_threshold = 40000;  in ni_dpm_init()
4136 		eg_pi->mclk_edc_wr_enable_threshold = 40000;  in ni_dpm_init()
4138 	ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;  in ni_dpm_init()
4140 	pi->voltage_control =  in ni_dpm_init()
4143 	pi->mvdd_control =  in ni_dpm_init()
4146 	eg_pi->vddci_control =  in ni_dpm_init()
4151 	pi->asi = RV770_ASI_DFLT;  in ni_dpm_init()
4152 	pi->pasi = CYPRESS_HASI_DFLT;  in ni_dpm_init()
4153 	pi->vrc = CYPRESS_VRC_DFLT;  in ni_dpm_init()
4155 	pi->power_gating = false;  in ni_dpm_init()
4157 	pi->gfx_clock_gating = true;  in ni_dpm_init()
4159 	pi->mg_clock_gating = true;  in ni_dpm_init()
4160 	pi->mgcgtssm = true;  in ni_dpm_init()
4161 	eg_pi->ls_clock_gating = false;  in ni_dpm_init()
4162 	eg_pi->sclk_deep_sleep = false;  in ni_dpm_init()
4164 	pi->dynamic_pcie_gen2 = true;  in ni_dpm_init()
4166 	if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)  in ni_dpm_init()
4167 		pi->thermal_protection = true;  in ni_dpm_init()
4169 		pi->thermal_protection = false;  in ni_dpm_init()
4171 	pi->display_gap = true;  in ni_dpm_init()
4173 	pi->dcodt = true;  in ni_dpm_init()
4175 	pi->ulps = true;  in ni_dpm_init()
4177 	eg_pi->dynamic_ac_timing = true;  in ni_dpm_init()
4178 	eg_pi->abm = true;  in ni_dpm_init()
4179 	eg_pi->mcls = true;  in ni_dpm_init()
4180 	eg_pi->light_sleep = true;  in ni_dpm_init()
4181 	eg_pi->memory_transition = true;  in ni_dpm_init()
4183 	eg_pi->pcie_performance_request =  in ni_dpm_init()
4186 	eg_pi->pcie_performance_request = false;  in ni_dpm_init()
4189 	eg_pi->dll_default_on = false;  in ni_dpm_init()
4191 	eg_pi->sclk_deep_sleep = false;  in ni_dpm_init()
4193 	pi->mclk_stutter_mode_threshold = 0;  in ni_dpm_init()
4195 	pi->sram_end = SMC_RAM_END;  in ni_dpm_init()
4197 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;  in ni_dpm_init()
4198 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in ni_dpm_init()
4199 	rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;  in ni_dpm_init()
4200 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);  in ni_dpm_init()
4201 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;  in ni_dpm_init()
4202 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in ni_dpm_init()
4203 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in ni_dpm_init()
4204 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;  in ni_dpm_init()
4206 	ni_pi->cac_data.leakage_coefficients.at = 516;  in ni_dpm_init()
4207 	ni_pi->cac_data.leakage_coefficients.bt = 18;  in ni_dpm_init()
4208 	ni_pi->cac_data.leakage_coefficients.av = 51;  in ni_dpm_init()
4209 	ni_pi->cac_data.leakage_coefficients.bv = 2957;  in ni_dpm_init()
4211 	switch (rdev->pdev->device) {  in ni_dpm_init()
4217 		ni_pi->cac_weights = &cac_weights_cayman_xt;  in ni_dpm_init()
4224 		ni_pi->cac_weights = &cac_weights_cayman_pro;  in ni_dpm_init()
4231 		ni_pi->cac_weights = &cac_weights_cayman_le;  in ni_dpm_init()
4235 	if (ni_pi->cac_weights->enable_power_containment_by_default) {  in ni_dpm_init()
4236 		ni_pi->enable_power_containment = true;  in ni_dpm_init()
4237 		ni_pi->enable_cac = true;  in ni_dpm_init()
4238 		ni_pi->enable_sq_ramping = true;  in ni_dpm_init()
4240 		ni_pi->enable_power_containment = false;  in ni_dpm_init()
4241 		ni_pi->enable_cac = false;  in ni_dpm_init()
4242 		ni_pi->enable_sq_ramping = false;  in ni_dpm_init()
4245 	ni_pi->driver_calculate_cac_leakage = false;  in ni_dpm_init()
4246 	ni_pi->cac_configuration_required = true;  in ni_dpm_init()
4248 	if (ni_pi->cac_configuration_required) {  in ni_dpm_init()
4249 		ni_pi->support_cac_long_term_average = true;  in ni_dpm_init()
4250 		ni_pi->lta_window_size = ni_pi->cac_weights->l2_lta_window_size;  in ni_dpm_init()
4251 		ni_pi->lts_truncate = ni_pi->cac_weights->lts_truncate;  in ni_dpm_init()
4253 		ni_pi->support_cac_long_term_average = false;  in ni_dpm_init()
4254 		ni_pi->lta_window_size = 0;  in ni_dpm_init()
4255 		ni_pi->lts_truncate = 0;  in ni_dpm_init()
4258 	ni_pi->use_power_boost_limit = true;  in ni_dpm_init()
4261 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ni_dpm_init()
4262 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in ni_dpm_init()
4263 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in ni_dpm_init()
4264 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ni_dpm_init()
4273 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in ni_dpm_fini()
4274 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in ni_dpm_fini()
4276 	kfree(rdev->pm.dpm.ps);  in ni_dpm_fini()
4277 	kfree(rdev->pm.dpm.priv);  in ni_dpm_fini()
4278 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in ni_dpm_fini()
4289 	r600_dpm_print_class_info(rps->class, rps->class2);  in ni_dpm_print_power_state()
4290 	r600_dpm_print_cap_info(rps->caps);  in ni_dpm_print_power_state()
4291 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ni_dpm_print_power_state()
4292 	for (i = 0; i < ps->performance_level_count; i++) {  in ni_dpm_print_power_state()
4293 		pl = &ps->performance_levels[i];  in ni_dpm_print_power_state()
4294 		if (rdev->family >= CHIP_TAHITI)  in ni_dpm_print_power_state()
4296 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);  in ni_dpm_print_power_state()
4299 			       i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);  in ni_dpm_print_power_state()
4308 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_debugfs_print_current_performance_level()
4315 	if (current_index >= ps->performance_level_count) {  in ni_dpm_debugfs_print_current_performance_level()
4318 		pl = &ps->performance_levels[current_index];  in ni_dpm_debugfs_print_current_performance_level()
4319 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ni_dpm_debugfs_print_current_performance_level()
4321 			   current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);  in ni_dpm_debugfs_print_current_performance_level()
4328 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_get_current_sclk()
4335 	if (current_index >= ps->performance_level_count) {  in ni_dpm_get_current_sclk()
4338 		pl = &ps->performance_levels[current_index];  in ni_dpm_get_current_sclk()
4339 		return pl->sclk;  in ni_dpm_get_current_sclk()
4346 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_get_current_mclk()
4353 	if (current_index >= ps->performance_level_count) {  in ni_dpm_get_current_mclk()
4356 		pl = &ps->performance_levels[current_index];  in ni_dpm_get_current_mclk()
4357 		return pl->mclk;  in ni_dpm_get_current_mclk()
4364 	struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);  in ni_dpm_get_sclk()
4367 		return requested_state->performance_levels[0].sclk;  in ni_dpm_get_sclk()
4369 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ni_dpm_get_sclk()
4375 	struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);  in ni_dpm_get_mclk()
4378 		return requested_state->performance_levels[0].mclk;  in ni_dpm_get_mclk()
4380 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ni_dpm_get_mclk()